ST72T311J2T6 STMicroelectronics, ST72T311J2T6 Datasheet - Page 24

• Manufacturer Part Number: ST72T311J2T6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST72T311J2T6

• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 5.5 V
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 6
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• On-chip Dac: No
• Program Memory Type: OTP EPROM
• Factory Pack Quantity: 160
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3 V

ST72E311 ST72T311
POWER SAVING MODES (Cont’d)
4.4.4 Halt Mode
The Halt mode is the MCU lowest power con-
sumption mode. The Halt mode is entered by exe-
cuting the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals. The Halt mode cannot be used when
the watchdog is enabled, if the HALT instruction is
executed while the watchdog system is enabled, a
watchdog reset is generated thus resetting the en-
tire MCU.
When entering Halt mode, the I bit in the CC Reg-
ister is cleared so as to enable External Interrupts.
If an interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of
an interrupt or a reset. Refer to the Interrupt Map-
ping Table. The oscillator is then turned on and a
stabilization time is provided before releasing CPU
operation. The stabilization time is 4096 CPU clock
cycles.
ation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
24/101
After the start up delay, the CPU continues oper-
24
Figure 19. HALT Flow Chart
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
1) or some specific interrupts
2) if reset PERIPH. CLOCK = ON ; if interrupt
WATCHDOG
N
PERIPH. CLOCK = OFF
RESET
INTERRUPT
EXTERNAL
Y
Y
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
1)
N
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
OSCILLATOR
PERIPH. CLOCK
CPU CLOCK
I-BIT
OR SERVICE INTERRUPT
FETCH RESET VECTOR
HALT INSTRUCTION
4096 CPU CLOCK
CYCLES DELAY
ENABLED?
RESET
WDG
Y
N
2)
OFF
OFF
OFF
CLEARED
OFF
ON
ON
SET
ON
ON
ON
SET