ST72T311J2T6 STMicroelectronics, ST72T311J2T6 Datasheet - Page 63

• Manufacturer Part Number: ST72T311J2T6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST72T311J2T6

• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 5.5 V
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 6
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• On-chip Dac: No
• Program Memory Type: OTP EPROM
• Factory Pack Quantity: 160
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3 V

SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 1.).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 1.).
BAUD RATE REGISTER (BRR)
Read/Write
Reset Value: 00xx xxxx (XXh)
Bit 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
SCP1
DR7
7
7
PR Prescaling factor
SCP0
DR6
13
SCT2
1
3
4
DR5
SCT1
DR4
SCT0
DR3
SCP1
SCR2
DR2
0
0
1
1
SCR1 SCR0
DR1
SCP0
0
1
0
1
DR0
0
0
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.
RR dividing factor
TR dividing factor
128
128
16
32
64
16
32
64
1
2
4
8
1
2
4
8
SCR2
SCT2
ST72E311 ST72T311
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SCR1
SCT1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
63
SCR0
SCT0
63/101
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1