ST72T311J2T6 STMicroelectronics, ST72T311J2T6 Datasheet - Page 25

• Manufacturer Part Number: ST72T311J2T6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/I2C
• Manufacturer: STMicroelectronics

Specifications of ST72T311J2T6

• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3 V to 5.5 V
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 6
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• On-chip Dac: No
• Program Memory Type: OTP EPROM
• Factory Pack Quantity: 160
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3 V

4.5 MISCELLANEOUS REGISTER
The Miscellaneous register allows to select the
SLOW operating mode, the polarity of external in-
terrupt requests and to output the internal clock.
Register Address: 0020h — Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = PEI[3:2] External Interrupt EI3 and EI2
Polarity Options .
These bits are set and cleared by software. They
determine which event on EI2 and EI3 causes the
external interrupt according to
Table 7. EI2 and EI3 External Interrupt Polarity
Note: Any modification of one of these two bits re-
sets the interrupt request related to this interrupt
vector.
Bit 5 = MCO Main Clock Out
This bit is set and cleared by software. When set, it
enables the output of the Internal Clock on the
PPF0 I/O port.
0 - PF0 is a general purpose I/O port.
1 - MCO alternate function (f
PEI3 PEI2 MCO PEI1 PEI0 PSM1 PSM0 SMS
pin).
7
Falling edge and low level
Rising and falling edge
Options
Falling edge only
Rising edge only
(Reset state)
MODE
CPU
Table
is output on PF0
7.
PEI3
0
1
0
1
PEI2
0
0
1
1
0
Bit 4:3 = PEI[1:0] External Interrupt EI1 and EI0
Polarity Options .
These bits are set and cleared by software. They
determine which event on EI0 and EI1 causes the
external interrupt according to
Table 8. EI0 and EI1 External Interrupt Polarity
Note: Any modification of one of these two bits re-
sets the interrupt request related to this interrupt
vector.
Bit 2:1 = PSM[1:0] Prescaler for Slow Mode
Table 9. f
Bit 0 = SMS Slow Mode Select
0: Normal Mode - f
1: Slow Mode - the f
This bit is set and cleared by software.
(Reset state)
PSM[1:0] bits.
Falling edge and low level
Rising and falling edge
These bits are set and cleared by soft-
ware. They determine the CPU clock
when the SMS bit is set according to the
following table.
Falling edge only
Rising edge only
Options
CPU
f
(Reset state)
CPU
f
f
f
OSC
f
OSC
MODE
OSC
OSC
Value in Slow Mode
Value
/ 16
/ 32
/ 4
/ 8
CPU
CPU
= f
value is determined by the
ST72E311 ST72T311
OSC
/ 2
Table
PSM1
PEI1
8.
0
0
1
1
0
1
0
1
25
PSM0
PEI0
25/101
0
1
0
1
0
0
1
1