M29W640GT70NA6E NUMONYX, M29W640GT70NA6E Datasheet - Page 19

• Manufacturer Part Number: M29W640GT70NA6E
• Description: IC FLASH 64MBIT 70NS 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W640GT70NA6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 23/22Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 8M/4M
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3
3.1
3.2
3.3
3.4
Bus operations
There are five standard bus operations that control the device. These are bus read, bus
write, output disable, standby and automatic standby. See
VIL
5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.
Bus read
Bus read operations read from the memory cells, or specific registers in the command
interface. A valid bus read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V
AC waveforms (8-bit
output becomes valid.
Bus write
Bus write operations write to the command interface. To speed up the read operation the
memory array can be read in page mode where data is internally read and stored in a page
buffer. The page has a size of 4 words and is addressed by the address inputs A0-A1.
A valid bus write operation begins by setting the desired address on the Address Inputs.
The Address Inputs are latched by the command interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the
command interface on the rising edge of Chip Enable or Write Enable, whichever occurs
first. Output Enable must remain High, V
Figure 15: Write AC waveforms, write enable controlled (8-bit
waveforms, chip enable controlled (8-bit
details of the timing requirements.
Output disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V
Standby
When Chip Enable is High, V
Inputs/Outputs pins are placed in the high-impedance state. To reduce the supply current to
the standby supply current, I
standby current level see
During program or erase operations the memory will continue to use the program/erase
supply current, I
and
Table 8: Bus operations, BYTE =
IH
CC3
. The Data Inputs/Outputs will output the value, see
, for program or erase operations until the operation completes.
mode), and
Table 17: DC
CC2
IH
, the memory enters standby mode and the Data
IL
, Chip Enable should be held within V
Table 18: Read AC
, to Chip Enable and Output Enable and keeping Write
characteristics.
IH
mode), and
VIH, for a summary. Typically glitches of less than
, during the whole bus write operation. See
Table 19: Write AC characteristics
characteristics, for details of when the
Table 7: Bus operations, BYTE =
mode),
Figure 13: Read mode
Figure 16: Write AC
CC
± 0.2 V. For the
19/90
for
IH
.