M29W640GT70NA6E NUMONYX, M29W640GT70NA6E Datasheet - Page 40

• Manufacturer Part Number: M29W640GT70NA6E
• Description: IC FLASH 64MBIT 70NS 48TSOP
• Manufacturer: NUMONYX
• Series: Axcell™r

Specifications of M29W640GT70NA6E

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 64M (8Mx8, 4Mx16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TSOP
• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 23/22Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 8M/4M
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Status register
Bus read operations from any address always read the status register during program and
erase operations. It is also read during erase suspend when an address within a block being
erased is accessed.
The bits in the status register are summarized in
Data polling bit (DQ7)
The data polling bit can be used to identify whether the program/erase controller has
successfully completed its operation or if it has responded to an erase suspend. The data
polling bit is output on DQ7 when the status register is read.
During program operations the data polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the program operation the memory
returns to read mode and bus read operations from the address just programmed output
DQ7, not its complement.
During erase operations the data polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the erase operation the memory returns to read
mode.
In erase suspend mode the data polling bit will output a ’1’ during a bus read operation
within a block being erased. The data polling bit will change from a ’0’ to a ’1’ when the
program/erase controller has suspended the erase operation.
Figure 9: Data polling
address is the address being programmed or an address within the block being erased.
Table 20: Reset/Block Temporary Unprotect AC characteristics
data polling operation and timings.
Toggle bit (DQ6)
The toggle bit can be used to identify whether the program/erase controller has successfully
completed its operation or if it has responded to an erase suspend. The toggle bit is output
on DQ6 when the status register is read.
During program and erase operations the toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive bus read operations at any address. After successful completion of the
operation the memory returns to read mode.
During erase suspend mode the toggle bit will output when addressing a cell within a block
being erased. The toggle bit will stop toggling when the program/erase controller has
suspended the erase operation.
Figure 10: Data toggle
Figure 20: Toggle/alternative toggle bit polling AC waveforms (8-bit mode)
description of the data polling operation and timings.
flowchart, gives an example of how to use the data polling bit. A valid
flowchart, gives an example of how to use the data toggle bit.
Table 13: Status register
gives a description of the
bits.
gives a