MT45W4MW16BFB-706 WT TR Micron Technology Inc, MT45W4MW16BFB-706 WT TR Datasheet
MT45W4MW16BFB-706 WT TR
Specifications of MT45W4MW16BFB-706 WT TR
Related parts for MT45W4MW16BFB-706 WT TR
MT45W4MW16BFB-706 WT TR Summary of contents
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... A15 DQ5 DQ6 G A13 DQ7 DQ15 A19 A12 WE# H A18 A8 A9 A10 A11 A20 J WAIT CLK ADV Top View (Ball Down) Designator Group 1.0 specification of -25°C. Part Number Example: MT45W4MW16BFB-708LWT ©2003 Micron Technology, Inc. All rights reserved. Features 6 8 None ...
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... Maximum and Typical Standby Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Timing Diagrams .37 Revision History .60 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAMTOC.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 Table of Contents ©2003 Micron Technology, Inc. All rights reserved. ...
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... Figure 47: Asynchronous WRITE Followed by Asynchronous READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Figure 48: 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAMLOF.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 TCR Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 List of Figures ©2003 Micron Technology, Inc. All rights reserved. ...
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... Table 46: READ Timing Parameters – Async WRITE Followed by Async READ . . . . . . . . . . . . . . . . . . . . . . . . . . .58 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAMLOT.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 4 List of Tables ©2003 Micron Technology, Inc. All rights reserved. ...
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... General Description Micron for low-power, portable applications. The MT45W4MW16BFB is a 64Mb DRAM core device organized as 4 Meg x 16 bits. This device includes an industry-standard burst mode Flash interface that dramatically increases read/write bandwidth compared with other low-power SRAM or Pseudo SRAM offerings. To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a trans- parent self refresh mechanism ...
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... Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a configuration register or to the memory array. Lower Byte Enable. DQ[7:0] Upper Byte Enable. DQ[15:8] Data Inputs/Outputs ...
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... When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence current. 7. DPD is maintained until RCR is reconfigured. 8. Burst mode operation is initialized through the bus configuration register (BCR[15]). PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 1 CLK ADV# CE# OE# WE ...
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... To view the location of the abbre- viated mark on the device, please refer to customer service note, CSN-11, “Product Mark/Label," at http://www.micron.com/csn. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory B FB -70 6 http://www.micron.com/partsearch Micron Technology, Inc ...
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... Functional Description In general, the MT45W4MW16BFB device is a high-density alternative to SRAM and Pseudo SRAM products, popular in low-power, portable applications. The MT45W4MW16BFB device contains a 67,108,864-bit DRAM core, organized as 4,194,304 addresses by 16 bits. The device implements the same high-speed bus inter- face found on burst mode Flash products. ...
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... WAIT will be driven while the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to HIGH. ADV must be driven LOW during all page mode read accesses. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory ADDRESS VALID DATA VALID READ Cycle Time < t CEM ...
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... CellularRAM device. The WAIT output will be asserted as soon as CE# goes LOW and will be de-asserted to indicate when data transferred into (or out of ) the memory. WAIT will again be asserted if the burst crosses the boundary between 128-word rows. Once the Cellular- RAM device has restored the previous row’ ...
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... Non-default BCR settings for burst mode WRITE (4-word burst): Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID Latency Code 2 (3 clocks) D[0] ...
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... CellularRAM device requires additional time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT transitions to an inactive state, the data burst will progress on successive clock edges ...
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... Non-default BCR settings for refresh collision during READ operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory D[0] Micron Technology, Inc., reserves the right to change products or specifications without notice. 14 ...
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... Non-default BCR settings for refresh collision during WRITE operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory D[0] Micron Technology, Inc., reserves the right to change products or specifications without notice. 15 ...
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... Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address map (see Table 6 on page 27) ...
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... WRITE operation when the control register enable (CRE) input is HIGH (see Figure 13 below and Figure 14 on page 18). When CRE is LOW, a READ or WRITE operation will access the memory array. The register values are placed on addresses A[21:0 asyn- chronous WRITE, the values are latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first ...
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... WAIT cycles caused by refresh collisions require a corresponding number of addi- tional CE# LOW cycles. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Latch Control Register Address Micron Technology, Inc., reserves the right to change products or specifications without notice. 18 ...
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... Figure 15: Load Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA Note: The WRITE on the third cycle must be CE#-controlled. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 1 READ READ WRITE ADDRESS ADDRESS ADDRESS (MAX) (MAX) (MAX) XXXXh ...
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... Notes: 1. The WRITE on the third cycle must be CE#-controlled. 2. CE# must be HIGH for 150ns before performing the cycle that reads a configuration regis- ter. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 1 READ READ WRITE ADDRESS ...
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... Bus Configuration Register The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the control bits in the BCR. At power-up, the BCR is set to 9D4Fh. The BCR is accessed using CRE and A[19] HIGH, or through the configuration register software sequence with DQ = 0001h on the third cycle ...
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... PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 8-Word 16-Word Burst Length Burst Length ...
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... The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during syn- chronous READ and WRITE operations. When BCR[ data will be valid or invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively (see Figure 18 and Figure 20) ...
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... V IH ADV DQ[15: DQ[15: PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory D[0] D[1] Code 2 VALID OUTPUT Code 3 (Default) 24 Configuration Registers BCR[ Data valid in current cycle. BCR[ Data valid in next cycle. D[2] D[3] D[4] DON’T CARE ...
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... The operating mode bit selects either synchronous burst operation or the default asyn- chronous mode of operation. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 25 Configuration Registers ...
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... Page Mode Disabled (default) 1 Page Mode Enable Maximum Case Temp. RCR[6] RCR[5] 1 +85˚C (default) 1 +70˚ +45˚ +15˚C 0 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory A19 A[18: 18– RESERVED PAGE TCR DPD Must be set to "0" RCR[4] 0 ...
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... Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This fea- ture allows the device to reduce standby current by refreshing only that part of the mem- ory array required by the host system. The refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array ...
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... Exposure to absolute maximum rating conditions for extended periods may affect reli- ability. Notes: 1. -30°C exceeds the CellularRAM Working Group 1.0 specification of -25°C. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Q Relative to V -0.50V to (4. Micron Technology, Inc ...
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... V slightly higher for up to 500ms after power-up or when entering standby mode. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 1 (-30ºC < T < +85ºC); Industrial Temperature (-40ºC < T ...
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... Maximum and Typical Standby Currents The following tables and figures refer to the maximum and typical standby currents for the MT45W4MW16BFB device. The typical values shown in Figure 23 on page 31 are measured with the appropriate PAR and TCR settings. The maximum values shown in Table 9 and Table 11 are measured with the relevant TCR bits set in the configuration register ...
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... Note: Typical I Table 11: Deep Power-Down Specifications Description Deep Power-Down PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory ) TCR Temperature (°C) currents for each PAR setting with the appropriate TCR selected. SB Conditions 0V; +25°C ...
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... Output Load Circuit DUT Note: All tests are performed with the outputs configured for full drive strength (BCR[5] = 0). Table 13: Output Load Circuit PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Conditions Symbol T = +25º MHz ...
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... Low-Z timings measure a 100mV transition away from the High-Z (V either V 4. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The High-Z timings measure a 100mV transition from either V PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Symbol AADV ...
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... High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The Low-Z timings measure a 100mV transition away from the High-Z (V either V PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory -708 Symbol Min t ABA ...
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... Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The High-Z timings measure a 100mV transition from either V 3. WE# LOW time must be limited to PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory Symbol AVH ...
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... Notes: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro- vided every tions: a) clocked CE# HIGH CE# HIGH for greater than 15ns. 2. Clock rates below 50 MHz ( PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory -708 Symbol Min t 5 ...
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... Vcc, VccQ = 1.70V Table 18: Initialization Timing Parameters Parameter Initialization Period (required before normal operations) PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t PU Symbol t PU Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... A[21:0] ADV# CE# LB#/UB# OE# WE# DQ[15:0] WAIT Table 19: Asynchronous READ Timing Parameters -70x Symbol Min Max Min BHZ 8 t BLZ 10 t CEW 1 7 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS OLZ BLZ High-Z ...
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... Asynchronous READ Timing Parameters Using ADV# -70x Symbol Min Max Min AADV t 5 AVH t AVS BHZ BLZ t CEW 1 7 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH VALID ADDRESS VPH t AVS t AVH AADV CVS OLZ V ...
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... Asynchronous READ Timing Parameters – Page Mode Operation -70x Symbol Min Max Min APA BHZ t BLZ 10 t CEM 8 t CEW 1 7 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS VALID VALID ADDRESS V ADDRESS CEM ...
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... ACLK BOE t 8 CEM t CEW 1 7.5 t CLK 12 4.5 20 CSP PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK CEM t t ABA BOE OHZ t OLZ t KHTL t KOH t ACLK VALID OUTPUT t CLK > 20ns) are allowed as long as ...
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... CEW 1 7 CLK t CSP 4 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t KHKL t CLK t CEM t ABA t BOE t OLZ t KHTL t ACLK VALID High-Z OUTPUT t CLK > 20ns) are allowed as long as -706/-856 Max Units Symbol t ...
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... CEW t 12 CLK t CSP 4 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK t CEM t ABA t BOE t OLZ t KHTL t KOH t ACLK VALID OUTPUT t CLK > 20ns) are allowed as long as -706/-856 Max Units Symbol t 56 ...
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... ACLK 9 t BOE CBPH t 8 CEM t CLK 12 CSP 4.5 20 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK t CEM t OHZ t BOE t KOH VALID VALID VALID VALID OUTPUT OUTPUT OUTPUT OUTPUT t CLK > 20ns) are allowed as long as ...
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... Burst READ Timing Parameters – BCR[ -708 Symbol Min Max Min t 9 ACLK t 12.5 20 CLK PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory NOTE 4 t KHTL NOTE 3 VALID OUTPUT t CLK > 20ns) are allowed as long as -706/-856 Max Units Symbol ...
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... LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 27: Asynchronous WRITE Timing Parameters – CE#-Controlled -70x Symbol Min Max Min CEW 1 7 CPH PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS WPH High WHZ V OH ...
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... LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 28: Asynchronous WRITE Timing Parameters – LB#/UB#-Controlled -70x Symbol Min Max Min 7.5 CEW PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS WPH High WHZ t LZ ...
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... ADV# CE# LB#/UB# OE# WE# DQ[15:0] IN DQ[15:0] OUT WAIT Table 29: Asynchronous WRITE Timing Parameters – WE#-Controlled -70x Symbol Min Max Min CEW 1 7 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS WPH High WHZ CEW ...
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... DQ[15:0] IN DQ[15:0] OUT WAIT Table 30: Asynchronous WRITE Timing Parameters Using ADV# -70x Symbol Min Max Min AVH t AVS 7.5 CEW PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory V IH VALID ADDRESS AVH t AVS VPH High ...
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... Min t CBPH 5 t CEM 8 t CEW 1 7.5 t 12.5 20 CLK t 4.5 20 CSP PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK CEM t KHTL D[0] t CLK > 20ns) are allowed as long as -706/-856 Max Units Symbol µs KHKL ...
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... Symbol Min Max Min t CLK 12 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory NOTE 4 t KHTL NOTE 3 VALID INPUT D[n+1] START OF ROW (NOTE 4) t CLK > 20ns) are allowed as long as -706/-856 Max Units Symbol t ...
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... Min t ABA 46 ACLK t 20 BOE t CLK 12 CSP 4.5 20 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t SP ADDRESS CBPH CSP D[0] D[1] D[2] D[ CEM. A refresh opportunity is satisfied by either of the following two condi- t CLK > 20ns) are allowed as long as ...
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... Symbol Min Max Min t ABA 46.5 t ACLK BOE t 5 CBPH t CEW 1 7.5 t CLK 12.5 20 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK CKA VALID VALID ADDRESS ADDRESS CSP t ABA t CBPH WPH t CEW V OH ...
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... Symbol Min Max Min t 46.5 ABA t ACLK 9 t BOE 20 t CBPH 7.5 CEW t CLK 12.5 20 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK CKA VALID ADDRESS CBPH t CSP t ABA CEW V OH DATA High CEM ...
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... Symbol Min Max Min PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK ABA t t BOE OHZ t OLZ t KHTL t KOH t ACLK VALID OUTPUT t CEM. A refresh opportunity is satisfied by either of the following two condi- Max Units Symbol ...
Page 56
... AVH AVS CEW 1 7 PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CLK t VPH ABA BOE OHZ t OLZ t KHTL t t ACLK KOH VALID OUTPUT t CEM. A refresh opportunity is satisfied by either of the following two condi- Max Units ...
Page 57
... READ Timing Parameters – ADV# LOW -70x Symbol Min Max Min BHZ t BLZ PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS CPH High-Z DATA CPH) to schedule the appropriate internal refresh operation. Otherwise, -856 Max Units Symbol ...
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... Max Min AADV t AVH 5 t AVS 10 t BHZ BLZ PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory VALID ADDRESS t AVH AVS CVS t CPH WPH V OH DATA DATA CPH) to schedule the appropriate internal refresh operation. Otherwise, ...
Page 59
... This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory 0.70 ±0.05 3.75 0.75 BALL A1 ID TYP 4.00 ± ...
Page 60
... Clarified READ/WRITE operating currents. • Added clarifying notes for required refresh opportunity for BCR[15], depending on BCR setting. • Changed PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory t CEM for async WRITES. 3 for READ and WRITE CPH to follow CE#-controlled async WRITE cycles only ...
Page 61
... Added V & L options. Modified WAIT in bus operations. Indicated wrap factors. • Added -706 part information where applicable. • Removed PDF: 09005aef80be1fbd/Source: 09005aef80be2036 Burst CellularRAM_2.fm - Rev. G 10/05 EN 64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory values and symbols Fig. 47 and Table 46. ...