MT45W4MW16BFB-706 WT TR Micron Technology Inc, MT45W4MW16BFB-706 WT TR Datasheet - Page 61

• Manufacturer Part Number: MT45W4MW16BFB-706 WT TR
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BFB-706 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/03
Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 09/03
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
• Updated I
• Added ADV# timing parameters and
• Clarified CE# LOW time limited by refresh—must not stay LOW longer than
• Aligned
• Added
• Deleted Appendix A (extended timings and all references).
• Added -708 timing specifications.
• Added C
• Clarified burst latency at row-boundary crossings.
• Replaced Abbreviated Component Marks with Part Numbering chart.
• Added measurement time clarification to I
• Changed
• Corrected package nomenclature to VFBGA.
• Clarified address A[4] and higher in page mode.
• Clarified CRE in Figure 14.
• Updated
• Changed BCR[6] = 0 to “not supported,” and deleted all references to falling clock
• Clarified mixed-mode operation.
• 104MHz part now “contact factory.”
• Changed
• Prohibited DPD via software access sequence.
• Changed
• Added “and ADV# LOW” to
• Added Note 6 to Tables 2 and 3 for Standby Mode, and clarified standby description
• -701 latency code 2 (3 clocks) changed to 66 MHz (15.2ns).
• Added lead-free option.
• Differentiated standard and low-power standby and related annotation in/for figures
• CLK in Tables 2 & 3 changed; can be either HIGH or LOW. Data and figures added to
• L, V and -60 now “contact factory.”
• Added V & L options. Modified WAIT in bus operations. Indicated wrap factors.
• Added -706 part information where applicable.
• Removed
Operation descriptions and timing diagrams.
edges.
27, 28, 34, 36, 37, 39, 41).
appropriate in Figures 34, 38, 41, 43, and corollary Tables 38, 44, 48.
under Low-Power Operation.
and tables.
cover software access to the configuration registers.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
t
CEM to Asynchronous WRITE, Page Mode READ Operation, and Burst Mode
t
IN
ACLK,
t
t
t
t
KP to 4ns for the -708, and 5ns for -706 and -856 parts.
CC
t
CBPH to
HD MIN in all speed grades to 2.
CSP (MIN) to 5ns for -706 and -856 in all burst timing tables (18, 20, 25, 26,
SP and
and C
values and symbols.
t
KHTL,
IO
t
HD from CE# in Burst diagrams.
t
MIN values.
CPH for async–async transitions.
t
ABA, and
61
t
AS in Async WRITE Timing Req. table; added
t
CSP with Workgroup values.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
CO to Fig. 47 and Table 46.
SB
and I
PAR
notes.
©2003 Micron Technology, Inc. All rights reserved.
Revision History
t
AS as
t
CEM.