MT45W4MW16BFB-706 WT TR Micron Technology Inc, MT45W4MW16BFB-706 WT TR Datasheet - Page 51

• Manufacturer Part Number: MT45W4MW16BFB-706 WT TR
• Description: IC PSRAM 64MBIT 70NS 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT45W4MW16BFB-706 WT TR

• Format - Memory: RAM
• Memory Type: PSRAM (Page)
• Memory Size: 64M (4M x 16)
• Speed: 70ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -30°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 40:
Table 32:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Symbol
t
t
CLK
HD
DQ[15:0]
LB#/UB#
A[21:0]
ADV#
WAIT
WE#
OE#
CLK
CE#
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
IH
IH
IL
IH
IL
IH
IL
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
Burst WRITE Timing Parameters – BCR[8] = 0
Continuous Burst WRITE Showing an Output Delay with BCR[8] = 0 for End-of-Row
Min
12.5
2
-708
Notes: 1. Non-default BCR settings for continuous burst WRITE, showing an output delay, with
t CLK
Max
20
t SP
INPUT D[n]
VALID
2. Clock rates below 50 MHz (
3. WAIT will be asserted a maximum of (2 x LC) + 1 cycles (BCR[8] = 0; WAIT asserted during
4. Taking CE# HIGH or ADV# LOW on the start-of-row cycle will abort the burst and not write
END OF ROW
t HD
Condition
BCR[8] = 0 for end-of-row condition: Latency code two (three clocks); WAIT active LOW;
WAIT asserted during delay.
delay). LC = Latency Code (BCR[13:11]).
the start-of-row data. Devices from different CellularRAM vendors can assert WAIT so that
the start-of-row data is input just before (as shown) or just after WAIT asserts. This differ-
ence in behavior will not be noticed by controllers that monitor WAIT or that use WAIT to
abort on the start-of-row input cycle.
Min
15
2
-706/-856
INPUT D[n+1]
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
VALID
START OF ROW
Max
20
(NOTE 4)
t KHTL
Units
ns
ns
NOTE 4
NOTE 3
t
51
CLK > 20ns) are allowed as long as
Symbol
t
t
KHTL
SP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Min
3
-708
Max
t KHTL
9
©2003 Micron Technology, Inc. All rights reserved.
t
CSP specifications are met.
INPUT D[n+2]
Min
-706/-856
3
Timing Diagrams
VALID
Max
11
DON’T CARE
INPUT D[n+3]
VALID
Units
ns
ns