MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet

MT47H64M8CB-3:B

Manufacturer Part Number

MT47H64M8CB-3:B

Description

IC DDR2 SDRAM 512MBIT 3NS 60FBGA

Manufacturer

Micron Technology Inc

Datasheet

1.MT47H64M8CB-5EB.pdf (133 pages)

Specifications of MT47H64M8CB-3:B

Format - Memory

RAM

Memory Type

DDR2 SDRAM

Memory Size

512M (64M x 8)

Speed

3ns

Interface

Parallel

Voltage - Supply

1.7 V ~ 1.9 V

Operating Temperature

0°C ~ 85°C

Package / Case

60-FBGA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

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Manufacturer

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Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

MT47H64M8CB-3:B

Manufacturer:

MICRON

Quantity:

12 388

Company:

BOSTOCK HK LIMITED

Part Number:

MT47H64M8CB-3:B

Manufacturer:

Micron Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

MT47H64M8CB-3:B TR

Manufacturer:

Micron Technology Inc

Quantity:

10 000

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DDR2 SDRAM

MT47H128M4 – 32 Meg x 4 x 4 banks

MT47H64M8 – 16 Meg x 8 x 4 banks

MT47H32M16 – 8 Meg x 16 x 4 banks

For the latest data sheet, refer to Micron’s Web site:

Features

• RoHS compliant

• V

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

• 4-bit prefetch architecture

• Duplicate output strobe (RDQS) option for x8

• DLL to align DQ and DQS transitions with CK

• 4 internal banks for concurrent operation

• Programmable CAS latency (CL)

• Posted CAS additive latency (AL)

• WRITE latency = READ latency – 1

• Programmable burst lengths: 4 or 8

• Adjustable data-output drive strength

• 64ms, 8,192-cycle refresh

• On-die termination (ODT)

• Industrial temperature (IT) option

• Supports JEDEC clock jitter specification

Table 1:

PDF: 09005aef8117c18e/Source: 09005aef8211b2e6

512MbDDR2_1.fm - Rev. K 8/06 EN

Architecture

Configuration 32 Meg x 4 x 4

Refresh Count

Row Addr.

Bank Addr.

Column Addr. 2K (A0–A9, A11) 1K (A0–A9)

= +1.8V ±0.1V, V

Configuration Addressing

Products and specifications discussed herein are subject to change by Micron without notice.

16K (A0–A13) 16K (A0–A13) 8K (A0–A12)

128 Meg x 4 64 Meg x 8 32 Meg x 16

4 (BA0–BA1) 4 (BA0–BA1) 4 (BA0–BA1)

banks

Q = +1.8V ±0.1V

16 Meg x 8 x

4 banks

8 Meg x 16 x

1K (A0–A9)

4 banks

http://www.micron.com/ddr2

Table 2:

Note: CL = CAS latency.

Options

• Configuration

• FBGA package (lead-free)

• Timing – cycle time

• Self refresh

• Operating temperature

• Revision

Speed

Grade

-37E

-25E

128 Meg x 4 (32 Meg x 4 x 4 banks)

64 Meg x 8 (16 Meg x 8 x 4 banks)

32 Meg x 16 (8 Meg x 16 x 4 banks)

5.0ns @ CL = 3 (DDR2-400)

3.75ns @ CL = 4 (DDR2-533)

3.0ns @ CL = 5 (DDR2-667)

3.0ns @ CL = 4 (DDR2-667)

2.5ns @ CL = 6 (DDR2-800)

2.5ns @ CL = 5 (DDR2-800)

Standard

Low-power

Commercial (0°C ≤ T

Industrial (–40°C ≤ T

-5E

-3E

-25

-3

Micron Technology, Inc., reserves the right to change products or specifications without notice.

84-ball FBGA (12mm x 12.5mm) (:B)

60-ball FBGA (12mm x 10mm) (:B)

CL = 3 CL = 4 CL = 5 CL = 6

400

N/A

512Mb: x4, x8, x16 DDR2 SDRAM

Key Timing Parameters

Data Rate (MHz)

N/A

400

533

667

533

(10mm x 12.5mm) (:D)

(10mm x 10mm) (:D)

≤ 95°C; –40°C ≤ T

≤ 85°C)

N/A

667

800

N/A

800

N/A

≤ 85°C)

(ns)

12.5

RCD

Marking

Features

(ns)

12.5

:A/:B/:D

128M4

32M16

64M8

None

-37E

-25E

-5E

-3E

-25

-3

(ns)

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