MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 41

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
Command
READ with
precharge
(Bank n)
From
auto
READ Using Concurrent Auto Precharge
Note:
WRITE or WRITE with auto precharge
READ or READ with auto precharge
Data from any READ burst must be completed before a subsequent WRITE burst is
allowed. An example of a READ burst followed by a WRITE burst is shown in Figure 24 on
page 43. The
time. (
A READ burst may be followed by a PRECHARGE command to the same bank, provided
that auto precharge was not activated. The minimum READ-to-PRECHARGE command
spacing to the same bank is AL + BL/2 clocks and must also satisfy a minimum analog
time from the rising clock edge that initiates the last 4-bit prefetch of a READ-to-
PRECHARGE command. This READ-to-PRECHARGE time is called
is the time from the actual READ (AL after the READ command) to PRECHARGE
command. For BL = 8 this is the time from AL + 2CK after the READ-to-PRECHARGE
command. Following the PRECHARGE command, a subsequent command to the same
bank cannot be issued until
Examples of READ-to-PRECHARGE are shown in Figure 22 on page 42 for BL = 4 and
Figure 23 on page 42 for BL = 8. The delay from READ-to-PRECHARGE command to the
same bank is AL + BL/2 + MAX (
If A10 is HIGH when a READ command is issued, the READ with auto precharge function
is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising edge,
which is AL + (BL/2) cycles later than the READ with auto precharge command if
(MIN) and
auto precharge operation will be delayed until
not satisfied at the edge, the start point of the auto precharge operation will be delayed
until
starts at the point where the internal precharge happens (not at the next rising clock
edge after this event). For BL = 4, the minimum time from READ with auto precharge to
the next ACTIVATE command becomes AL + (
page 42; for BL = 8, the time from READ with auto precharge to the next ACTIVATE
command is AL + 2 clocks + (
each parameter term is divided by
internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
Part of the row precharge time is hidden during the access of the last data elements.
PRECHARGE or ACTIVE
t
RTP (MIN) is satisfied. In case the internal precharge is pushed out by
t
To Command
DQSS [MIN] and
(Bank m)
t
RTP are satisfied. If
t
DQSS (MIN) case is shown; the
t
DQSS [MAX] are defined in Figure 31 on page 51.)
t
t
RP is met.
RTP +
41
t
t
RAS (MIN) is not satisfied at the edge, the start point of
RTP/
t
CK and rounded up to the next integer. In any event,
t
RP)*, shown in Figure 23 on page 42. The * indicates
t
CK or 2CK) - 2CK.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Concurrent Auto Precharge)
Minimum Delay (with
512Mb: x4, x8, x16 DDR2 SDRAM
t
t
DQSS (MAX) case has a longer bus idle
RTP +
t
RAS (MIN) is satisfied. If
(BL/2) + 2
BL/2
t
RP)*, shown in Figure 22 on
1
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t
RTP. For BL = 4 this
t
RTP (MIN) is
t
Units
RTP,
t
t
t
CK
CK
CK
READs
t
t
RAS
RP