MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 33

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
Minimum Delay with Auto Precharge Enabled
10. The number of clock cycles required to meet
4. REFRESH and LM commands may only be issued when all banks are idle.
5. Not used.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
8. Requires appropriate DM.
9. A WRITE command may be applied after the completion of the READ burst.
From Command
WRITE with auto
READ with auto
READ with
auto
precharge
enabled/
WRITE with
auto
precharge
enabled:
precharge enabled and READs or WRITEs with auto precharge disabled.
greater.
precharge
precharge
(Bank n)
The minimum delay from a READ or WRITE command with auto precharge
enabled to a command to a different bank is summarized in Table 8:
The READ with auto precharge enabled or WRITE with auto precharge
enabled states can each be broken into two parts: the access period and the
precharge period. For READ with auto precharge, the precharge period is
defined as if the same burst was executed with auto precharge disabled and
then followed with the earliest possible PRECHARGE command that still
accesses all of the data in the burst. For WRITE with auto precharge, the
precharge period begins when
precharge was disabled. The access period starts with registration of the
command and ends where the precharge period (or
supports concurrent auto precharge such that when a READ with auto
precharge is enabled or a WRITE with auto precharge is enabled, any
command to other banks is allowed, as long as that command does not
interrupt the read or write data transfer already in process. In either case, all
other related limitations apply (contention between read data and write data
must be avoided).
WRITE or WRITE with auto
WRITE or WRITE with auto
To Command (Bank m)
READ or READ with auto
READ or READ with auto
PRECHARGE or ACTIVE
PRECHARGE or ACTIVE
33
precharge
precharge
precharge
precharge
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
512Mb: x4, x8, x16 DDR2 SDRAM
WR ends, with
WTR is either 2 or
Concurrent Auto Precharge)
Minimum Delay (With
(CL - 1) + (BL / 2) +
Command Truth Tables
t
WR measured as if auto
(BL / 2) + 2
©2004 Micron Technology, Inc. All rights reserved.
t
(BL / 2)
(BL / 2)
WTR/
t
RP) begins. This device
1
1
t
CK, whichever is
t
WTR
Units
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK