MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 94

IC DDR2 SDRAM 512MBIT 3NS 60FBGA

MT47H64M8CB-3:B

Manufacturer Part Number
MT47H64M8CB-3:B
Description
IC DDR2 SDRAM 512MBIT 3NS 60FBGA
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT47H64M8CB-3:B

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
512M (64M x 8)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Table 28:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
(V/ns)
Slew
Rate
DQ
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
Δ
125
t
83
4.0 V/ns
0
DS Δ
DDR2-400/533
Notes: 1–7; all units in ps
t
45
21
0
DH Δ
Notes:
125
–11
3.0 V/ns
t
83
0
DS Δ
1. For all input signals, the total
2.
3.
4. Although the total setup time might be negative for slow slew rates (a valid input signal
5. For slew rates between the values listed in this table, the derating values may be obtained
6. These values are typically not subject to production test. They are verified by design and
7. Single-ended DQS requires special derating. The values in Table 30 are the DQS single-
–14
t
45
21
DH Δ
0
value to the derating value listed in Table 28.
t
of V
defined as the slew rate between the last crossing of V
V
shaded “V
the actual signal is later than the nominal slew rate line anywhere between shaded
“V
level to DC level is used for derating value (see Figure 72).
t
ing of V
nal is defined as the slew rate between the last crossing of V
of V
shaded “DC level to V
Figure 73). If the actual signal is earlier than the nominal slew rate line anywhere between
shaded “DC to V
DC level to V
will not have reached V
signal is still required to complete the transition and reach V
by linear interpolation.
characterization.
ended slew rate derating with DQS referenced at V
t
t
and
(
t
DS nominal slew rate for a rising signal is defined as the slew rate between the last crossing
DH nominal slew rate for a rising signal is defined as the slew rate between the last cross-
DS
DH
t
DS,
IL
DS
REF
(
b
AC
a
125
a
–11
–25
REF
REF
t
t
2.0 V/ns
83
) for DDR2-667. Table 32 provides the V
and
DH
0
DS Δ
(
and
t
) MAX. If the actual signal is always earlier than the nominal slew rate line between
DC
DH Derating Values with Differential Strobe
(
DC
(DC). If the actual signal is always later than the nominal slew rate line between
IL
a
) to AC region,” the slew rate of a tangent line to the actual signal from the AC
) for DDR2-533. Table 33 provides the V
(
t
) and the first crossing of V
DC
DH
t
REF
–14
–31
DH
t
45
21
DH Δ
0
) MAX and the first crossing of V
REF
(
b
a
DC
. Table 31 provides the V
) for DDR2-400.
(
DQS, DQS# Differential Slew Rate
) to AC region,” use nominal slew rate for derating value (see Figure 71). If
REF
DC
–13
–31
t
95
12
1.8 V/ns
1
DS Δ
) level is used for derating value (see Figure 74).
(
DC
REF
) region,” the slew rate of a tangent line to the actual signal from the
–19
–42
t
IH
33
12
–2
DH Δ
(
DC
(
AC
) region,” use nominal slew rate for derating value (see
)/V
94
–19
–43
t
1.6 V/ns
t
24
13
–1
DS and
DS Δ
IL
(
AC
) at the time of the rising clock transition), a valid input
–30
–59
t
24
10
–7
IH
DH Δ
t
(
REF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DH required is calculated by adding the data sheet
AC
) MIN.
-based fully derated values for the DQ (
–31
–74
t
25
11
1.4 V/ns
–7
DS Δ
REF
REF
512Mb: x4, x8, x16 DDR2 SDRAM
-based fully derated values for the DQ (
(
t
DC
REF
–18
–47
–89
t
DS nominal slew rate for a falling signal is
22
5
DH Δ
).
REF
-based fully derated values for the DQ
t
DH nominal slew rate for a falling sig-
and DQ referenced at the logic levels
–127 –140 –115 –128 –103 –116
REF
–19
–62
1.2 V/ns
t
23
Input Slew Rate Derating
5
DS Δ
(
DC
IH
) and the first crossing of
IH
–35
–77
(
t
17
–6
DC
(
DH Δ
AC
©2004 Micron Technology, Inc. All rights reserved.
) MIN and the first crossing
)/V
–50
IL
t
17
1.0 V/ns
–7
DS Δ
(
AC
).
–23
–65
t
6
DH Δ
–38
0.8 V/ns
t
t
5
DS Δ
DS
a
and
t
–11
–53
t
DS
DH
a

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