ISL6549CAZA-T Intersil, ISL6549CAZA-T Datasheet - Page 14

• Manufacturer Part Number: ISL6549CAZA-T
• Description: IC CTRLR PWM SYNC BUCK 16-QSOP
• Manufacturer: Intersil

Specifications of ISL6549CAZA-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1MHz
• Duty Cycle: 100%
• Voltage - Supply: 4.75 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-QSOP
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL6549CAZA-TTR

FET is particularly slow in these parameters, there is a greater
chance that shoot-through current will occur.
As referenced in the “Block Diagram” on page 2, the UGATE
signal is referenced to PHASE signal. The deadtime
comparator also looks at the difference (UGATE - PHASE).
This is significant when viewing the gate driver waveforms on
an oscilloscope. One simple indication of shoot-through (or
insufficient deadtime) is when the UGATE and LGATE signals
overlap. But in this case, one should look at UGATE-PHASE
(either by a math function of the two signals, or by using a
differential probe measurement) compared to LGATE.
Figure 12 shows an example of this. It looks as if the UGATE
and LGATE signals have crossed, but the UGATE-PHASE
signal does not cross the LGATE.
One important consideration is negative spikes on the PHASE
node as it goes low. The upper FET is turning off, but before
the lower FET can take over, stray inductance in the layout
(on the board, or even the inductance of some components,
such as D
negative.
There is no maximum spec for PHASE spike below GND,
however, there is an absolute maximum rating for
(BOOT - PHASE) of 7V; exceeding this limit can cause
damage to the IC, and possibly to the system. Since the
BOOT signal is typically 5V above the PHASE node most of
the time, it only takes a few volts of a spike on either signal to
exceed the limit. A good design should be characterized by
using the math function or differential probe, and monitoring
these signals for compliance, especially during full loads,
where the signals are usually the noisiest. Slowing down the
turn-off of the upper FET may help, while at other times,
sometimes the problem may just be the choice of FETs.
If the power efficiency of the system is important, then other
FET parameters are also considered. Efficiency is a measure
of power losses from input to output, and it contains two major
components: losses in the IC (mostly in the gate drivers) and
losses in the FETs. Optimizing the sum involves many
trade-offs (for example, raising the voltage of the gate drivers
GND>
GND>
GND>
GND>
UGATE (4V/DIV)
PHASE (4V/DIV)
UGATE-PHASE (4V/DIV)
2
FIGURE 12. GATE DRIVER WAVEFORMS
PAK FETs) can contribute to the PHASE going
14
LGATE (4V/DIV)
ISL6549
typically adds power to the IC side, but may reduce some
power on the FET side). For low duty cycle applications (such
as 12V in to 1.5V out), the upper FET is usually chosen for low
gate charge, since switching losses are key, while the lower
FET is chosen for low R
For high duty cycles (such as 3.3V in to 2.5V out), the
opposite is true.
In summary, the following parameters may need to be
considered in choosing the right FETs for an application:
drain-source breakdown voltage rating, gate-source rating,
maximum current, thermal and package considerations, low
gate threshold voltage, gate charge, R
switching speed. And, of course, the board layout constraints
and cost also are factored into the decision.
Linear FET Considerations
The linear FET is chosen primarily for thermal performance.
The current for the linear output is generally limited by the
power dissipation (P = (V
thermal rating for getting the heat out of the package, and
spreading it out on the board, especially when no heatsinks or
airflow is available. It is generally not recommended to parallel
two FETs in order to get higher current or to spread out the
heat, as the FETs would need to be very well-matched in
order to share the current properly. Should this approach be
desired, and as perfectly matched FETs are seldom available,
a small resistor, or PCB trace of suitable resistance placed in
the source of each of the FETs can be used to improve the
current balance.
The maximum V
several factors:
• Power dissipation, as described earlier
• Input voltage available
• LDO_DR voltage
• FET chosen
The voltage cannot be any higher than the input voltage
available, and the max V
The LDO_DR voltage is driven from the VCC12 rail; allowing
for headroom, the typical maximum voltage is 11V (lower as
VCC12 goes to its minimum of 10.8V). So the maximum
output voltage will be at least a V
FET threshold voltage) below the 11V, at the maximum load
current; some additional headroom is usually needed to
handle transient conditions. So a practical typical value
around 8V may be possible, but remember to also factor in
the variations for worst case conditions on V
parameters. As long as the V
headroom versus VCC12 is not a problem, then the maximum
output voltage is just below V
at maximum current.
The input supply for V
less than 12V, subject to the considerations above. The
drain-source breakdown voltage of the FET should be greater
OUT2
IN2
voltage allowed is determined by
DS(ON)
IN2
IN2
can also be any available supply
is 12V (13.2V for a ±10% supply).
- V
IN2
IN2
, since it is on most of the time.
OUT2
, based on the R
GS
is low enough such that
drop (which includes the
) * I), and the FET
DS(ON)
IN2
at 4.5V, and
September 22, 2006
and the FET
DS(ON)
FN9168.2
drop