ISL6549CAZA-T Intersil, ISL6549CAZA-T Datasheet - Page 15

• Manufacturer Part Number: ISL6549CAZA-T
• Description: IC CTRLR PWM SYNC BUCK 16-QSOP
• Manufacturer: Intersil

Specifications of ISL6549CAZA-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 2
• Frequency - Max: 1MHz
• Duty Cycle: 100%
• Voltage - Supply: 4.75 V ~ 13.2 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-QSOP
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL6549CAZA-TTR

than the V
greater than 12V (even though the output voltage may not
require such a high gate voltage, load transients or other
disturbances might force LDO_DR to momentarily approach
12V). The FET threshold is not critical, except for the cases
where the LDO_DR headroom is diminished. And finally, the
package (and board area allowed) must be able to handle the
maximum power dissipation expected.
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching converter
design. With power devices switching efficiently at 600kHz,
the resulting current transitions from one device to another
cause voltage spikes across the interconnecting impedances
and parasitic circuit elements. These voltage spikes can
degrade efficiency, radiate noise into the circuit, and lead to
device overvoltage stress. Careful component layout and
printed circuit board design minimizes the voltage spikes in
the converters.
As an example, consider the turn-off transition of the PWM
upper MOSFET. Prior to turn-off, the MOSFET is carrying the
full load current. During turn-off, current stops flowing in the
upper MOSFET and is picked up by the lower MOSFET and
parasitic diode. Any parasitic inductance in the switched
current path generates a large voltage spike during the
switching interval. Careful component selection, tight layout of
the critical components, and short, wide traces minimizes the
magnitude of voltage spikes.
There are two sets of critical components in a DC/DC converter
using the ISL6549. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
A multilayer printed circuit board is recommended. Figure 13
shows the connections of the critical components in the
converter. Capacitors C
numerous physical capacitors. Dedicate one solid layer,
usually a middle layer of the PC board, for a ground plane and
make all critical component ground connections through vias
to this layer. Dedicate another solid layer as a power plane
and break this plane into smaller islands of common voltage
levels. Keep the metal runs from the PHASE terminal to the
output inductor short. The power plane should support the
input and output power nodes. Use copper filled polygons on
the top and bottom circuit layers for the phase node. Use the
remaining printed circuit layers for small signal wiring. The
wiring traces from the LGATE and UGATE pins to the
MOSFET gates should be kept short and wide enough to
easily handle the several Amps of drive current.
The critical small signal components include any bypass
capacitors, feedback components, and compensation
IN2
voltage. The FET’s gate-source rating should be
IN
and C
15
OUT
could each represent
ISL6549
components. Position the bypass capacitors, C
close to their pins with a local GND connection, or via directly
to the ground plane. R12 should be placed near VCC5 and
PVCC5 pins. FS_DIS resistor R7 should be near the FS-DIS
pin, and its GND return should be short, and kept away from
the noisy FET GND. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors for both regulators should also be located as close
as possible to the relevant FB pin with vias tied straight to the
ground plane as required.
Then the switching components should be placed close to the
ISL6549. Minimize the length of the connections between the
input capacitors, C
nearby. Position both the ceramic and bulk input capacitors as
close to the upper MOSFET drain as possible, and make the
GND returns (from lower FET source to VIN cap GND) short.
Position the output inductor and output capacitors between
the upper MOSFET and lower MOSFET and the load.
References
Applications Note: AN1201
Visit us on the internet: www.intersil.com
FIGURE 13. PRINTED CIRCUIT BOARD POWER PLANES
VCC12
PVCC5
VCC5
R12
C
R
C
C
4
7
6
5
GND
VCC12
PVCC5
PGND
GND
VCC5
FS_DIS
ISL6549
AND ISLANDS
KEY
LDO_DR
LDO_FB
PHASE
LGATE
IN
UGATE
COMP
BOOT
, and the power switches by placing them
VIA CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
FB
R
C
C
2
2
7
R6
R
4
R5
C
1
V
C
IN1
3
Q1
Q2
R1
R
3
C
C
L
OUT2
Q3
OUT
IN1
C
V
4
OUT1
September 22, 2006
IN2
, C
C
V
5
IN2
OUT1
, and C
FN9168.2
V
OUT2
6