ISL6551IR-T Intersil, ISL6551IR-T Datasheet - Page 13

• Manufacturer Part Number: ISL6551IR-T
• Description: IC CTRL PWM ZVS FULL BRDG 28-QFN
• Manufacturer: Intersil

Specifications of ISL6551IR-T

• Pwm Type: Current Mode
• Number Of Outputs: 6
• Frequency - Max: 1MHz
• Duty Cycle: 50%
• Voltage - Supply: 10.8 V ~ 13.2 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

• Leading Edge Blanking (R_LEB)
- In current mode control, the sensed switch (FET) current is
processed in the Ramp Adjust and LEB circuits and then
compared to a control signal (EAO voltage). Spikes, due to
parasitic elements in the bridge circuit, would falsely trigger
the comparator generating the PWM signal. To prevent
false triggering, the leading edge of the sensed current
signal is blanked out by a period that can be programmed
with the R_LEB resistor. Internal switches gate the analog
input to the PWM comparator, implementing the blanking
function that eliminates response degrading delays which
would be caused if filtering of the current feedback was
399K
500
450
400
350
300
250
200
150
100
50
R_RA
R_LEB
0
0.1µ
+37%
ISENSE
FIGURE 7. R_RESDLY vs RESDLY
R_LEB
R_RA
20
+4%
BGREF
VDD
40
FIGURE 9. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
R_RESDLY (kΩ)
ADD RAMP
BLANKING
13
TIME
SET
60
RESDLY
(See Fig. 4)
80
ADJ_RAMP
LEB
SSL
100
+18%
-24%
200mV
120
ISL6551
-
+
RAMP_OUT
(TO PWM
COMPARATOR)
- The blanking time can be estimated with Equation 9,
incorporated. The current ramp is blanked out during the
resonant delay period because no switching occurs in the
lower FETs. The leading edge blanking function will not be
activated until the soft-start (CSS) reaches over 400mV, as
illustrated in Figures 4 and 9. The leading edge blanking
(LEB) function can be disabled by tying the R_LEB pin to
VDD, i.e., LEB=1. Never leave the pin floating.
whose relationship can be seen in Figure 8. The
percentages in the figure are the tolerances at the two
endpoints of the curve.
t
300
250
200
150
100
LEB
50
0
20
RESDLY
= 2 x R_LEB / k
+51%
X
0
1
1
-11%
200mV
200mV
40
RAMP_OUT
FIGURE 8. R_LEB vs t
0
LEB
X
X
0
1
Ω
60
ADJ_RAMP
+ 15 (ns)
ISENSE
R_LEB (kΩ)
SSL
X
X
0
1
80
BLANK
RAMP_OUT
LEB
NO BLANK
NO BLANK
100
BLANK
BLANK
120
+20%
January 3, 2006
-18%
(EQ. 9)
FN9066.5
140