LT3837EFE#TRPBF Linear Technology, LT3837EFE#TRPBF Datasheet - Page 18

• Manufacturer Part Number: LT3837EFE#TRPBF
• Description: IC CNTRLR SYNC ISO 16TSSOP
• Manufacturer: Linear Technology
• Type: Flybackr

Specifications of LT3837EFE#TRPBF

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Frequency - Switching: 50kHz ~ 250kHz
• Voltage - Input: 4.5 ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Output: -
• Power - Output: -

LT3837
APPLICATIONS INFORMATION
Enable Delay Time (ENDLY)
Enable delay time provides a programmable delay between
turn-off of the primary gate drive node and the subsequent
enabling of the feedback amplifi er. As discussed earlier, this
delay allows the feedback amplifi er to ignore the leakage
inductance voltage spike on the primary side.
The worst-case leakage spike pulse width is at maximum
load conditions. So set the enable delay time at these
conditions.
While the typical applications for this part use forced
continuous operation, it is conceivable that a secondary-
side controller might cause discontinuous operation at
light loads. Under such conditions the amount of energy
stored in the transformer is small. The fl yback waveform
becomes “lazy” and some time elapses before it indicates
the actual secondary output voltage. The enable delay time
should be made long enough to ignore the “irrelevant”
portion of the fl yback waveform at light load.
Even though the LT3837 has a robust gate drive, the gate
transition-time slows with very large MOSFETs. Increase
delay time is as required when using such MOSFETs.
The enable delay resistor is set with the following equa-
tion:
Keep R
is 56k.
Primary Gate Delay Time (PGDLY)
Primary gate delay is the programmable time from the
turn-off of the synchronous MOSFET to the turn-on of
the primary side MOSFET. Correct setting eliminates
overlap between the primary side switch and secondary
side synchronous switch(es) and the subsequent current
spike in the transformer. This spike will cause additional
component stress and a loss in regulator effi ciency.
18
R
ENDLY
ENDLY
(
k
Ω =
greater than 40k. A good starting point
)
t
ENDLY
2 616
.
( ) –
ns
30
The primary gate delay resistor is set with the following
equation:
A good starting point is 27k.
Soft-Start Functions
The LT3837 contains an optional soft-start function that is
enabled by connecting an external capacitor between the
SFST pin and ground. Internal circuitry prevents the control
voltage at the V
There is an initial pull-up circuit to quickly bring the SFST
voltage to approximately 0.8V. From there it charges to
approximately 2.8V with a 20μA current source.
The SFST node is then discharged to 0.8V when a fault
occurs. A fault is V
current sense voltage greater than 200mV or the IC’s
thermal (overtemperature) shutdown is tripped. When
SFST discharges, the V
to below the minimum current voltage. Once discharged,
the SFST recharges up again.
In this manner, switch currents are reduced and the stresses
in the converter are reduced during fault conditions.
The time it takes to fully charge soft-start is:
UVLO Pin Function
The UVLO pin provides a user programming undervoltage
lockout. This is usually used to provide undervoltage
lockout based on V
UVLO is below the 1.24V UVLO threshold. An external
resistive divider between the input supply and ground is
used to set the turn-on voltage.
The bias current on this pin depends on the pin volt-
age and UVLO state. The change provides the user with
adjustable UVLO hysteresis. When the pin rises above
the UVLO threshold a small current is sourced out of the
pin, increasing the voltage on the pin. As the pin voltage
drops below this threshold, the current is stopped, further
R
t
SS
PGDLY
=
C
SFST
(
k
Ω =
20
)
C
μA
• .
pin from exceeding that on the SFST pin.
1 4
t
PGDLY
IN
V
CC
. The gate drivers are disabled when
=
C
too low (undervoltage lockout),
9 01
70
( )
.
node voltage is also pulled low
ns
ms C
+ 47
•
SFST
( )
μF
3837fc