PCM18XK1 Microchip Technology, PCM18XK1 Datasheet - Page 258

• Manufacturer Part Number: PCM18XK1
• Description: MODULE PROC PIC18F8680,6680,8565
• Manufacturer: Microchip Technology

Specifications of PCM18XK1

• Accessory Type: Processor Module
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• For Use With/related Products: ICE2000
• For Use With: ICE2000 - EMULATOR MPLAB-ICE 2000 POD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
19.6
Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set and the ACQT2:ACQT0
bits are cleared. A conversion is started after the follow-
ing instruction to allow entry into Sleep mode before the
conversion begins.
Figure 19-4 shows the operation of the A/D converter
after the GO bit has been set, the ACQT2:ACQT0 bits
are set to ‘010’ and selecting a 4 T
before the conversion starts.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D Result register
pair will not be updated with the partially completed A/D
conversion sample. This means the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers).
After the A/D conversion is completed or aborted, a
2 T
be started. After this wait, acquisition on the selected
channel is automatically started.
FIGURE 19-3:
FIGURE 19-4:
DS30491C-page 256
Note:
(Holding capacitor continues
acquiring input)
AD
Set GO bit
1
wait is required before the next acquisition can
T
Set GO bit
CY
A/D Conversions
Holding capacitor is disconnected from analog input (typically 100 ns)
T
ACQT
- T
Acquisition
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Automatic
2
AD
Time
Conversion starts
Cycles
T
AD
3
1 T
A/D CONVERSION T
A/D CONVERSION T
AD
b9
4
2 T
Conversion starts
(Holding capacitor is disconnected)
AD
b8
1
3 T
AD
acquisition time
AD
b9
b7
2
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
4 T
Next Q4: ADRESH:ADRESL is loaded, GO bit is cleared,
AD
b8
3
b6
AD
AD
5 T
ADIF bit is set, holding capacitor is connected to analog input.
CYCLES (A
CYCLES (A
ADIF bit is set, holding capacitor is reconnected to analog input.
AD
b5
b7
4
6 T
AD
T
b4
5
b6
AD
7 T
Cycles
19.7
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared), the
“special event trigger” will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
CQT
CQT
AD
b3
b5
6
8
<2:0> = 000, T
<2:0> = 010, T
T
AD
Use of the CCP2 Trigger
b4
b2
7
9 T
AD
b3
b1
8
10
T
ACQ
AD
b0
b2
ACQ
9
 2004 Microchip Technology Inc.
11
= 0)
= 4 T
10
b1
AD
b0
11
)