TMP86C993XB Toshiba, TMP86C993XB Datasheet
TMP86C993XB
Specifications of TMP86C993XB
Related parts for TMP86C993XB
TMP86C993XB Summary of contents
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Bit Microcontroller TLCS-870/C Series TMP86FH92DMG ...
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... TOSHIBA products could cause loss of human life, bodily injury or damage to property.In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSH- IBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Sem- iconductor Devices,” ...
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... Precaution for debugging the Flash control register Although the TMP86FH92DMG contains the Flash control register (FLSCR) at 0FFFH in the DBR area, the TMP86C993XB do not contain the FLSCR register. Therefore, when using the development tool for debugging, a program that accesses the FLSCR register cannot function properly (executes differently as in the case of TMP86FH92DMG) ...
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Difference among Products ・ Differences in Functions Producrs CPUCORE ROM RAM Interrrupt I/O Port 0 Port 1 Port 2 Port 3 Watchdog Timer Timer/counter UART (1 channel is shared with I Serial bus interface (I C bus) SDA(P13) and ...
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Date Revision 2007/4/19 1 2007/5/17 2 2007/6/26 3 2008/1/31 4 2008/2/27 5 2008/9/26 6 Revision History First Release Contents Revised Contents Revised Contents Revised Contents Revised Contents Revised ...
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Table of Contents Precaution for Using the Emulation Chip / Difference among Products TMP86FH92DMG 1.1 Features......................................................................................................................................1 1.2 Pin Assignment..........................................................................................................................3 1.3 Block Diagram...........................................................................................................................4 1.4 Pin Names and Functions..........................................................................................................5 2. Operational Description 2.1 CPU Core Functions .................................................................................................................7 2.1.1 Memory Address Map ........................................................................................................................................................7 ...
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Saving/restoring general-purpose registers .......................................................................................................................39 3.3.2.1 Using PUSH and POP instructions 3.3.2.2 Using data transfer instructions 3.3.3 Interrupt return ..................................................................................................................................................................42 3.4 Software Interrupt (INTSW) ...................................................................................................42 3.4.1 Address error detection .....................................................................................................................................................42 3.4.2 Debugging .........................................................................................................................................................................43 3.5 Undefined Instruction Interrupt (INTUNDEF) ......................................................................43 3.6 ...
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Watchdog Timer Reset .....................................................................................................................................................73 8.3 Address Trap ...........................................................................................................................74 8.3.1 Selection of Address Trap in Internal RAM (ATAS) .......................................................................................................74 8.3.2 Selection of Operation at Address Trap (ATOUT) ..........................................................................................................74 8.3.3 Address Trap Interrupt (INTATRAP)...............................................................................................................................74 8.3.4 Address Trap Reset............................................................................................................................................................75 9. Time Base ...
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Data Sampling Method........................................................................................................122 12.6 STOP Bit Length.................................................................................................................123 12.7 Parity....................................................................................................................................123 12.8 Transmit/Receive Operation................................................................................................123 12.8.1 Data Transmit Operation...............................................................................................................................................123 12.8.2 Data Receive Operation.................................................................................................................................................123 12.9 Status Flag...........................................................................................................................124 12.9.1 Parity Error....................................................................................................................................................................124 12.9.2 Framing Error................................................................................................................................................................124 12.9.3 Overrun Error.................................................................................................................................................................124 12.9.4 Receive Data Buffer Full...............................................................................................................................................125 12.9.5 Transmit ...
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Write collision error.......................................................................................................................................................145 14.8.2 Overflow error ..............................................................................................................................................................145 14.8.3 Mode fault error ............................................................................................................................................................146 14.9 Bus Driver Protection .........................................................................................................146 15. Serial Bus Interface Bus) Ver.-D (SBI) 15.1 Configuration ......................................................................................................................147 15.2 Control ................................................................................................................................147 15.3 Software Reset.....................................................................................................................147 15.4 The Data Format ...
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Control.................................................................................................................................174 18. Flash Memory 18.1 Flash Memory Control.........................................................................................................176 18.1.1 Flash Memory Command Sequence Execution Control (FLSCR<FLSMD>)..............................................................176 18.1.2 Flash Memory Standby Control (FLSSTB<FSTB>).....................................................................................................176 18.2 Command Sequence............................................................................................................178 18.2.1 Byte Program.................................................................................................................................................................178 18.2.2 Sector Erase (4-kbyte Erase)..........................................................................................................................................178 18.2.3 Chip Erase (All Erase)...................................................................................................................................................179 18.2.4 ...
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Input/Output Circuitry 20.1 Control Pins.........................................................................................................................215 20.2 Input/Output Ports...............................................................................................................216 21. Electrical Characteristics 21.1 Absolute Maximum Ratings................................................................................................219 21.2 Operating Conditions...........................................................................................................220 21.2.1 MCU mode (Flash Programming or erasing) ...............................................................................................................220 21.2.2 MCU mode (Except Flash Programming or erasing) ...................................................................................................220 21.2.3 Serial PROM mode........................................................................................................................................................221 ...
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viii ...
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... TOSHIBA or the third parties. 070122_C ・For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S CMOS 8-Bit Microcontroller ROM RAM Package (FLASH) 16384 512 SSOP30-P-56-0.65 bytes bytes Page 1 TMP86FH92DMG Emulation Chip TMP86C993XB ...
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Features Pulse width modulation (PWM) output, Programmable pulse generation (PPG), 16bit mode (8bit timer 2ch combination) modes 10. 8-bit UART : 2 ch 11. 8bit Serial Expansion Interface (SEI): 1 channel (MSB/LSB selectable and max. 4Mbps at 16MHz) 12. ...
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Pin Assignment (XTIN) P21 (XTOUT) P22 (INT5/STOP) P20 (TXD1) P00 (BOOT/RXD1) P01 (SCLK) P02 (MOSI) P03 (MISO) P04 (SS) P05 VSS P37 (AIN5/STOP5) XIN P36 (AIN4/STOP4) XOUT P35 (AIN3/STOP3) TEST P34 (AIN2/STOP2) VDD P33 (AIN1) P32 (AIN0) P31 (TC4/PDO4/PWM4/PPG4) ...
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Block Diagram 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86FH92DMG ...
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Pin Names and Functions The TMP86FH92DMG has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin ...
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Pin Names and Functions Table 1-1 Pin Names and Functions (2/2) Pin Name P37 AIN5 STOP5 P36 AIN4 STOP4 P35 AIN3 STOP3 P34 AIN2 STOP2 P33 AIN1 P32 AIN0 P31 TC4 PDO4/PWM4/PPG4 P30 TC3 PDO3/PWM3 XIN XOUT RESET TEST ...
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Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset ...
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System Clock Controller The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to “00H”. (TMP86FH92DMG SRAMCLR: LD INC ...
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High-frequency clock XIN XOUT XIN (a) Crystal/Ceramic (b) External oscillator resonator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, ...
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System Clock Controller SYSCK DV7CK High-frequency 1 2 clock fc Low-frequency clock fs Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions Main system clock generator ...
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Timing Generator Control Register TBTCR (0036H) (DVOEN) (DVOCK) Selection of input to the 7th stage of DV7CK the divider Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1” ...
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System Clock Controller (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2<IDLE> ...
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Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. ...
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System Clock Controller 2.2.3.4 Operating Mode Transition IDLE1 mode (a) Single-clock mode IDLE2 mode SLEEP2 mode SLEEP1 mode (b) Dual-clock mode Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 ...
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Table 2-1 Operating Mode and Conditions Oscillator Operating Mode High Low Frequency Frequency RESET NORMAL1 Oscillation Single IDLE1 Stop clock IDLE0 STOP Stop NORMAL2 IDLE2 Oscillation SLOW2 Oscillation Dual SLEEP2 clock SLOW1 SLEEP1 Stop SLEEP0 STOP Stop AD CPU Core ...
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System Clock Controller 2.2.4 Operating Mode Control System Control Register 1 SYSCR1 7 6 (0038H) STOP RELM STOP STOP mode start Release method for STOP RELM mode Operating mode after STOP RETM mode OUTEN Port output during STOP mode ...
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Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to “1” simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal ...
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System Clock Controller Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST JRS LD DI SET SINT5: RETI STOP pin XOUT pin NORMAL operation Note 1: Even if the STOP pin input is low ...
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STOP mode is released by the following sequence the dual-clock mode, when returning to NORMAL2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to SLOW1 mode, only the low- frequency clock oscillator is ...
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System Clock Controller Figure 2-9 STOP Mode Start/Release Page 20 TMP86FH92DMG ...
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IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is ...
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System Clock Controller ・ Start the IDLE1/2 and SLEEP1/2 modes and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”. ・ Release the IDLE1/2 and SLEEP1/2 modes These modes are selected by interrupt master enable flag ...
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Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 23 TMP86FH92DMG ...
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System Clock Controller 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and ...
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Start the IDLE0 and SLEEP0 mode s Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 mode s, set SYSCR2<TGHALT> to “1”. ・ Release the IDLE0 and SLEEP0 mode s IDLE0 and SLEEP0 mode s ...
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System Clock Controller Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 26 TMP86FH92DMG ...
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SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2<SYSCK> to switch ...
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System Clock Controller (2) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2<SYSCK> to switch the main ...
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Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 29 TMP86FH92DMG ...
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Reset Circuit 2.3 Reset Circuit The TMP86FH92DMG has types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset, voltage detect reset 1,voltage detection 2,power on reset, trimming ...
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VDD RESET 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or SFR ...
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Reset Circuit 2.3.5 Power-on Reset A power-on reset is generated internally when the supply voltage (VDD) is turned on. Refer to Section “Power on reset”. 2.3.6 Voltage detection reset A voltage detection reset is generated internally when the supply ...
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Internal Reset Detection Flags After an internal reset is released, the cause of this internal reset can be identified by reading the internal reset detection flag register (IRSCR). IRSCR<SYSRSF> corresponds to system clock reset, IRSCR<ADTRF> to address trap reset, ...
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Internal Reset Detection Flags Page 34 TMP86FH92DMG ...
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Interrupt Control Circuit The TMP86FH92DMG has a total of 22 interrupt sources excluding reset. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt ...
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Interrupt latches (IL21 to IL2) 3.1 Interrupt latches (IL21 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch ...
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The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized ...
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Interrupt Sequence Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after ...
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Interrupt request Interrupt latch (IL) IMF Execute Execute Interrupt acceptance instruction instruction a − Note 1: a: Return address, b: Entry address, c: Address which RETI instruction is stored Note ...
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Interrupt Sequence 3.3.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP ...
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Main task Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing Interrupt Interrupt service task acceptance Saving registers Restoring registers Interrupt return Page 41 TMP86FH92DMG ...
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Software Interrupt (INTSW) 3.3.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. As for address trap interrupt (INTATRAP required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] ...
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The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM, DBR ...
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External Interrupts 3.7 External Interrupts The TMP86FH92DMG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with ...
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External Interrupt Control Register EINTCR (0037H) INT1NC INT0EN INT3ES INT1NC Noise reject time select INT0EN P10/INT0 pin configuration INT4 ES INT4 edge select INT3 ES INT3 edge select INT1 ES INT1 edge select Note 1: fc: High-frequency ...
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External Interrupts Page 46 TMP86FH92DMG ...
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Special Function Register (SFR) The TMP86FH92DMG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address ...
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SFR Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Note 1: Do not access reserved areas by the program. Note ...
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DBR Address 0F80H : : 0F9FH Address 0FA0H : : 0FBFH Address 0FC0H : : 0FDFH Address 0FE0H 0FE1H 0FE2H 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH 0FF0H 0FF1H 0FF2H 0FF3H 0FF4H 0FF5H ...
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DBR Address 0FFFH Note 1: Do not access reserved areas by the program. Note 2: − ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, ...
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I/O Ports The TMP86FH92DMG have 4 parallel input/output ports as follows. Primary Function Port P0 8-bit I/O port Port P1 5-bit I/O port Port P2 3-bit I/O port Port P3 8-bit I/O port Each output port contains a latch, ...
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P0 (P07 to P00) Port (High Current) 5.1 P0 (P07 to P00) Port (High Current) The P0 port is an 8-bit input/output port shared with external interrupt input, serial expansion interface input/output, UART1 input/output, timer counter input/output and serial ...
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P0DR P07 P06 P05 P04 (0000H) TC1 INT3 SS MISO R/W INT4 PPG P0OUTCR (000BH) R/W P0 port input/output control P0OUTCR (specified bitwise P0PUCR (0004H) R/W P0 port pull-up resistance con- ...
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P1 (P14 to P10) Port 5.2 P1 (P14 to P10) Port The P1 port is a 5-bit input/output port shared with external interrupt input, divider output, UART2 input/output and serial bus interface input/output. When using this port as divider ...
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P1DR P14 (0001H) TXD2 R/W SCL P1OUTCR (0009H) R/W P1port input/output control P1OUTCR (specified bitwise P1PUCR (0005H) R/W P1 port pull-up resistance control P1PUCR (specified bitwise P1PRD (002DH) ...
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P2 (P22 to P20) Port 5.3 P2 (P22 to P20) Port The P2 port is a 3-bit input/output port shared with external interrupt input, STOP mode release signal input, and low-frequency resonator connecting pin. When using this port as ...
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P2DR (0002H) R P2PUCR (0006H) R/W P2 port pull-up resistance con- P2PUCR trol (specified bitwise P2PRD (000DH) Read only Note:The P20 pin is shared with the STOP pin, so that when ...
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P3 (P37 to P30) Port 5.4 P3 (P37 to P30) Port The P3 port is an 8-bit input/output port that can be specified for input or output bitwise, and is shared with analog input and key-on wakeup input (KWI). ...
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Control input OUTEN P3CR1k D Q P3CR1k Data input (P3DRk Data output (P3DRk Output latch Control output a) Equivalent circuit of P30, P31 D Q P3CR2i D Q P3CR2i input D Q ...
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P3 (P37 to P30) Port 7 6 P37 P36 P3DR AIN5 AIN4 (0003H) STOP5 STOP4 R P3CR1 (0008H) Controls P3 port input/output P3CR1 (specified bitwise P3CR2 (000AH) Controls P3 port input (specified P3CR2 bitwise) Note ...
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... Note:The power-on reset circuit cannot be emulated with the TMP86C993XB (Emulation Chip). Therefore, when using the development tool for debugging, ensure that operation is performed within the operating voltage range of the TMP86FH92DMG ...
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Power-on reset circuit Supply operating voltage PROFF V PRON Power-on reset signal Warm-up counter clock CPU/peripheral circuits reset signal Note 1: The power-on reset circuit may not operate properly depending on transitions in supply voltage (VDD). ...
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Voltage detection circuit (VLTD) The voltage detecting circuit monitors the supply voltage level and generates an interrupt or reset upon detection of a low-voltage condition. Note:The voltage detecting circuit may not operate properly depending on transitions in supply voltage ...
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... The functions of the VDCR1 and VDCR2 vary between the TMP86FH92DMG and the emulation chip TMP86C993XB. For details, refer to the register descriptions below. The TMP86C993XB does not allow an interrupt or a reset to be generated by voltage detection. Instead, the VD1S and VD2S bits are provided in the VDCR2 to support the emulation of voltage detection operation. Setting VDCR2< ...
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... Voltage detection 2 disable 1: Voltage detection 2 enable 0: INTVLTD interrupt 1: Voltage detection 1 reset signal occurrence 0: Voltage detection 1 disable 1: Voltage detection 1 enable Page 65 TMP86FH92DMG 0 （Initial value: **** 0000) TMP86C993XB 0: Generate a reset or an inter- Write rupt by VD2 Only - 1: 0: Generate a reset or an inter- Write rupt by VD1 Only - 1: ...
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Function 7.3 Function The voltage detecting circuit allows two threshold voltage levels (VDxLVL specified. For each threshold voltage, whether to enable or disable voltage detect operation and the action to be taken when ...
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When VDCR2<VDxEN>=1, a drop of the supply voltage (VDD) below the threshold voltage (VDxLVL) causes the VDCR1<VDxF> flag to be set. This flag remains set until it is cleared by software. VDCR1<VDxF> is not cleared to 0 when the supply ...
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Setting of register To disable the voltage detection circuit while it is enabled with the voltage detection interrupt request, make the following setting: 1. Clear the INTVLTD interrupt enable flag <EF4> Clear VDCR2<VDxEN> ...
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Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog ...
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Watchdog Timer Control 8.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 8.2.1 Malfunction Detection Methods Using the Watchdog Timer ...
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Watchdog Timer Control Register WDTCR1 (0034H) (ATAS) WDTEN Watchdog timer enable/disable WDTT Watchdog timer detection time [s] WDTOUT Watchdog timer output select Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”. ...
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Watchdog Timer Control 8.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the micro controller. 1. Set the interrupt master ...
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Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset time is maximum ...
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Address Trap 8.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register WDTCR1 (0034H) Select address trap generation in ATAS ...
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Address Trap Reset While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the ...
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Address Trap Page 76 TMP86FH92DMG ...
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Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 9.1 Time Base Timer 9.1.1 Configuration MPX 23 15 fc/2 or fs/2 21 ...
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Time Base Timer Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN = "0"). (The interrupt fre- quency must not be changed with the disable from the enable state.) Both frequency selection ...
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Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. 9.2.1 Configuration Output latch Data output D Q MPX 13 5 ...
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Divider Output (DVO) Example :1.95 kHz pulse output (fc = 16.0 MHz Table 9-2 Divider Output Frequency ( Example : fc = 16.0 MHz 32.768 kHz ) DVOCK Setting port (TBTCR) , 00000000B (TBTCR) , ...
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Timer/Counter 1 (TC1) 10.1 Configuration Figure 10-1 TimerCounter 1 (TC1) Page 81 TMP86FH92DMG ...
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Timer/Counter Control 10.2 Timer/Counter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Timer Register 15 14 TC1DRA (0011H, 0010H) TC1DRB (0013H, 0012H) TimerCounter 1 Control Register ...
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Note 3: To set the mode, source clock, PPG output control and timer F/F control, write to TC1CR during TC1S=00. Set the timer F/F1 control until the first timer start after setting the PPG mode. Note 4: Auto-capture can be ...
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Function 10.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 10.3.1 Timer mode In the timer mode, the up-counter counts up using the ...
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Timer start Source clock Counter 0 1 TC1DRA ? INTTC1 interruput request Source clock m − − 1 Counter m − 1 TC1DRB ? ACAP1 Figure 10-2 Timer Mode Timing Chart n − ...
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Function 10.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge ...
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Count start TC1 pin input Source clock Up-counter TC1DRA INTTC1 interrupt request Count start TC1 pin input Source clock Up-counter TC1DRA INTTC1 interrupt request Figure 10-3 External Trigger Timer Mode Timing Chart ...
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Function 10.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the ...
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Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the ...
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Function 10.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or ...
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Example :Duty measurement (resolution fc/2 CLR LD DI SET PINTTC1: CPL JRS RETI SINTTC1 RETI : VINTTC1: DW TC1 pin INTTC1 interrupt request INTTC1SW [Hz INTTC1 service switch ...
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Function TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request Count start Trigger (a) Single-edge capture Count start 0 1 ...
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Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. To start the timer, TC1CR<TC1S> specifies either the edge of the input pulse ...
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Function Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG ( MHz) LD LDW LDW TC1CR<TFF1> Write to TC1CR Internal reset Match to TC1DRB Match to ...
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Timer start Internal clock Counter TC1DRB n Match detect TC1DRA m PPG pin output INTTC1 interrupt request Count start Trigger TC1 pin input Internal clock Counter TC1DRB m TC1DRA PPG pin output ...
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Function Page 96 TMP86FH92DMG ...
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TimerCounter (TC3, TC4) 11.1 Configuration 11 3 fc fc/2 16-bit mode TC4 pin S TC4M ...
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TimerCounter Control 11.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 7 6 (001CH) R/W PWREG3 7 6 (001EH) R/W Note ...
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Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 11-3. Note 8: The clock "fc" can be selected as the source clock only in 8/16 bit PWM mode and ...
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TimerCounter Control The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 7 6 (001DH) R/W PWREG4 7 6 (001FH) R/W Note 1: Do ...
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Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 11-1 and Table 11-2. Note 8: The timer register settings are limited depending on the timer operating mode. For the ...
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TimerCounter Control Table 11-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 16-bit PPG Note Register Value 1≤ (TTREGn) ≤255 1≤ ...
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Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16- ...
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Function TC4CR<TC4S> Internal Source Clock Counter TTREG4 ? INTTC4 interrupt request 11.3.2 8-Bit Event Counter Mode (TC3 the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj ...
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Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port LD (TTREG4), 3DH LD (TC4CR), 00010001B LD (TC4CR), 00011001B Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is ...
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Function Figure 11-4 8-Bit PDO Mode Timing Chart (TC4) Page 106 TMP86FH92DMG ...
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Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with bits of resolution. The up- counter counts up using the internal clock. When a match ...
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Function Figure 11-5 8-Bit PWM Mode Timing Chart (TC4) Page 108 TMP86FH92DMG ...
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Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer ...
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Function TC4CR<TC4S> Internal source clock Counter 0 TTREG3 ? (Lower byte) TTREG4 ? (Upper byte) INTTC4 interrupt request Figure 11-6 16-Bit Timer Mode Timing Chart (TC3 and TC4) 11.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event ...
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Since PWREG4 and 3 in the PWM mode are serially connected to the shift register, the values set to PWREG4 and 3 can be changed while the timer is running. The values set to PWREG4 and 3 during a run ...
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Function Figure 11-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 112 TMP86FH92DMG ...
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Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascadable to enter the 16-bit PPG mode. The counter ...
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Function Figure 11-8 16-Bit PPG Mode Timing Chart (TC3 and TC4) Page 114 TMP86FH92DMG ...
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Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16- ...
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Function 11.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set ...
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Asynchronous Serial interface (UART1) 12.1 Configuration UART control register 1 UART1CR1 3 2 INTTXD1 INTRXD1 S fc/13 A fc/26 B fc/52 C fc/104 D Y fc/208 E fc/416 F INTTC3 G fc/96 H Baud rate generator Figure 12-1 UART1 ...
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Control 12.2 Control UART1 is controlled by the UART1 Control Registers (UART1CR1, UART1CR2). The operating status can be monitored using the UART status register (UART1SR). UART1 Control Register1 7 6 UART1CR1 (0025H) TXE RXE TXE Transfer operation RXE Receive ...
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UART1 Control Register2 UART1CR2 (0026H) Selection of RXD input noise RXDNC rejection time STOPBR Receive stop bit length Note:Settings of RXDNC are limited depending on the transfer clock specified by BRG. The combination "Ο" is avail- ...
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Control UART1 Transmit Data Buffer 7 6 TD1BUF (0027H Page 120 TMP86FH92DMG Write only (Initial value: 0000 0000) ...
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Transfer Data Format In UART1, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UART1CR1<STBT>), and parity (Select parity in UART1CR1<PE>; even- or odd-numbered parity by UART1CR1<EVEN>) are added to the transfer data. ...
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Transfer Rate 12.4 Transfer Rate The baud rate of UART1 is set of UART1CR1<BRG>. The example of the baud rate are shown as follows. Table 12-1 Transfer Rate (Example) BRG 000 001 010 011 100 101 When TC3 is ...
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STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UART1CR1<STBT>. 12.7 Parity Set parity / no parity by UART1CR1<PE> and set parity type (Odd- or Even-numbered) by UART1CR1<EVEN>. 12.8 Transmit/Receive Operation 12.8.1 Data ...
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Status Flag 12.9 Status Flag 12.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART1SR<PERR> is set to “1”. The UART1SR<PERR> is cleared to “0” when the ...
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UART1SR<RBFL> RXD1 pin Shift register RD1BUF UART1SR<OERR> INTRXD1 interrupt Figure 12-7 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UART1SR<OERR> is cleared. 12.9.4 Receive Data Buffer Full Loading the received data in RD1BUF sets receive ...
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Status Flag TD1BUF xxxx ***** 1 Shift register TXD1 pin UART1SR<TBEP> INTTXD1 interrupt Figure 12-9 Generation of Transmit Data Buffer Empty 12.9.6 Transmit End Flag When data are transmitted and no data is in TD1BUF (UART1SR<TBEP> = “1”), transmit ...
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Asynchronous Serial interface (UART2) 13.1 Configuration UART control register 1 UART2CR1 3 2 INTTXD2 INTRXD2 S fc/13 A fc/26 B fc/52 C fc/104 D Y fc/208 E fc/416 F INTTC3 G fc/96 H Baud rate generator Figure 13-1 UART2 ...
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Control 13.2 Control UART2 is controlled by the UART2 Control Registers (UART2CR1, UART2CR2). The operating status can be monitored using the UART status register (UART2SR). UART2 Control Register1 7 6 UART2CR1 (0022H) TXE RXE TXE Transfer operation RXE Receive ...
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UART2 Control Register2 UART2CR2 (0023H) Selection of RXD input noise RXDNC rejection time STOPBR Receive stop bit length Note:Settings of RXDNC are limited depending on the transfer clock specified by BRG. The combination "Ο" is avail- ...
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Control UART2 Transmit Data Buffer 7 6 TD2BUF (0024H Page 130 TMP86FH92DMG Write only (Initial value: 0000 0000) ...
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Transfer Data Format In UART2, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UART2CR1<STBT>), and parity (Select parity in UART2CR1<PE>; even- or odd-numbered parity by UART2CR1<EVEN>) are added to the transfer data. ...
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Transfer Rate 13.4 Transfer Rate The baud rate of UART2 is set of UART2CR1<BRG>. The example of the baud rate are shown as follows. Table 13-1 Transfer Rate (Example) BRG 000 001 010 011 100 101 When TC3 is ...
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STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UART2CR1<STBT>. 13.7 Parity Set parity / no parity by UART2CR1<PE> and set parity type (Odd- or Even-numbered) by UART2CR1<EVEN>. 13.8 Transmit/Receive Operation 13.8.1 Data ...
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Status Flag 13.9 Status Flag 13.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART2SR<PERR> is set to “1”. The UART2SR<PERR> is cleared to “0” when the ...
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UART2SR<RBFL> RXD2 pin Shift register RD2BUF UART2SR<OERR> INTRXD2 interrupt Figure 13-7 Generation of Overrun Error Note:Receive operations are disabled until the overrun error flag UART2SR<OERR> is cleared. 13.9.4 Receive Data Buffer Full Loading the received data in RD2BUF sets receive ...
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Status Flag TD2BUF xxxx ***** 1 Shift register TXD2 pin UART2SR<TBEP> INTTXD2 interrupt Figure 13-9 Generation of Transmit Data Buffer Empty 13.9.6 Transmit End Flag When data are transmitted and no data is in TD2BUF (UART2SR<TBEP> = “1”), transmit ...
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Serial Expansion Interface (SEI) SEI is one of the serial interfaces incorporated in the TMP86FH92DMG. It allows connection to peripheral devices via full-duplex synchronous communication protocols. The TMP86FH92DMG contain one channel of SEI. SEI is connected with an external ...
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SEI Registers 14.2 SEI Registers The SEI interface has the SEI Control Register (SECR), SEI Status Register (SESR), and SEI Data Register (SEDR) which are used to set up the SEI system and enable/disable SEI operation. 14.2.1 SEI Control ...
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Slave mode When the SEI is operating as a slave, the serial clock is input from the master and the setting of the SER bit has no effect. The maximum transfer rate is fc/4. Note:Take note of the following ...
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SEI Operation 14.3 SEI Operation During a SEI transfer, data transmission (serial shift-out) and reception (serial shift-in) are performed simultane- ously. The serial clock synchronizes the timing at which information on the two serial data lines are shifted or ...
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SEI Pin Functions The TMP86FH92DMG have four input/output pins associated with SEI transfer. The functionality of each pin depends on the SEI device’s mode (master or slave). The SCLK pin, MOSI pin and MISO pin of all SEI devices ...
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SEI Transfer Formats 14.5 SEI Transfer Formats The transfer formats are set using CPHA and CPOL (SECR<CPHA,CPOL>). CPHA allows transfer protocols to be selected between two. 14.5.1 CPHA (SECR register bit format Figure 14-2 shows a ...
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CPHA = 1 format Figure 14-3 shows a transfer format when CPHA = 1. SCLK Cycle 1 SCLK (CPOL = 0) SCLK (CPOL = 1) MOSI MISO SS SEF Figure 14-3 Transfer Format When CPHA = 1 Table 14-5 ...
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Functional Description 14.6 Functional Description Figure 14-4 shows how the SEI master and slave are connected. When the master device sends data from its MOSI pin to a slave device’s MOSI pin, the slave device returns data from its ...
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Interrupt Generation The TMP86FH92DMG is provided with the SEI interrupt channels 0 and 1 (INTSEI0 and INTSEI1) for processing SEI interrupts. INTSEI0 generates an interrupt pulse when the SESR<MODF> flag is set. INTSEI1 generates an interrupt pulse when the ...
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Bus Driver Protection 14.8.3 Mode fault error When the SEI device is set as the master, a mode fault error occurs if the SS pin is driven low. When a mode fault error occurs, the SEI immediately performs the ...
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Serial Bus Interface(I The TMP86FH92DMG has a serial bus interface which employs an I The serial interface is connected to an external devices through SDA and SCL. The serial bus interface pins are also used as the port. When ...
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The Data Format in the I C Bus Mode 2 15.4 The Data Format in the I The data format of the I (a) Addressing format S Slave address (b) Addressing format (with restart) S Slave address (c) Free ...
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Bus Control The following registers are used to control the serial bus interface and monitor the operation status of the I Serial Bus Interface Control Register SBICRA (0015H Number of transferred ...
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I C Bus Control bus Address Register 7 I2CAR (0017H) SA6 SA Slave address selection Address recognition mode spec- ALS ification Note 1: I2CAR is write-only register, which cannot be used with any of read-modify-write ...
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Serial Bus Interface Status Register SBISRB (0018H) MST TRX BB Master/slave selection status MST monitor Transmitter/receiver selection TRX status monitor BB Bus status monitor Interrupt service requests status PIN monitor AL Arbitration lost detection monitor Slave ...
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I C Bus Control 2 Table 15-1 SCL and SDA Pins Status in Acknowledgement Mode Mode Master Slave SDA 15.5.1.2 Non-acknowledgment mode (ACK = “0”) To set the device as a non-acknowledgement mode, the ACK (Bit4 in SBICRA) should ...
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HIGH n t LOW = 2 / HIGH = 2 /fc + 8/fc fscl = 1/( t LOW + t HIGH) t SCKL t SCKH t SCKL , t SCKH > 4 tcyc Note ...
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I C Bus Control 2 The clock pulse on the bus is determined by the master device with the shortest high-level period and the master device with the longest low-level period from among those master devices connected to the ...
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SCL pin A6 SDA pin Start condition Figure 15-5 Start Condition Generation and Slave Address Generation When the BB is “1”, sequence of generating a stop condition is started by writing “1” to the MST, TRX and PIN, and ...
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I C Bus Control 2 15.5.9 Setting of I The SBIM (Bit3 and 2 in SBICRB) is used to set I Set the SBIM to “10” in order to set I pins in a high level, and then, write ...
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SCL pin Master A D7A D6A D5A D4A SDA pin 1 SCL pin Master B D7B D6B SDA pin AL MST TRX Accessed to SBIDBR or SBICRB INTSBI Figure 15-8 Example of when a Serial Bus Interface Circuit is ...
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Data Transfer Bus 2 After confirming that the serial bus interface pin is high level, for specifying the default setting to a slave receiver mode, clear “0” to the MST, TRX and BB in SBICRB, set ...
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When the LRB is “0”, the receiver requests next data. When the next transmitted data is other than 8 bits, set the BC, set the ACK to “1”, and write the transmitted data to the SBIDBR. After writing the data, ...
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Data Transfer Bus 2 SCL pin SDA pin PIN INTSBI interrupt request Figure 15-12 Termination of Data Transfer in Master Receiver Mode 15.6.3.2 When the MST is “0” (Slave mode) In the slave mode, a serial ...
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Table 15-4 Operation in the Slave Mode TRX AL AAS AD0 1 1 1/0 Note:In the slave mode, if the slave address set ...
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Data Transfer Bus 2 15.6.5 Restart Restart is used to change the direction of data transfer between a master device and a slave device during transferring data. The following explains how to restart a serial bus ...
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AD Converter (ADC) The TMP86FH92DMG have a 10-bit successive approximation type AD converter. 16.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 16-1. It consists of control register ADCCR1 and ADCCR2, converted value ...
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Register configuration 16.2 Register configuration The AD converter consists of the following four registers converter control register 1 (ADCCR1) This register selects the analog channels and operation mode (Software start or repeat) in which to perform AD ...
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AD Converter Control Register ADCCR2 (000FH) IREFON DA converter (Ladder resistor) connection IREFON control AD conversion time select ACK (Refer to the following table about the con- version time) Note 1: Always set bit0 in ADCCR2 ...
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Register configuration AD Converted value Register 2 7 ADCDR2 (0020H) AD01 EOCF ADBF Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therefore, the AD conversion result should be read to ADCDR2 more first than ADCDR1. ...
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Function 16.3.1 Software Start Mode After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conversion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started. After completion of the AD conversion, ...
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Function ADCCR1<AMD> ADCCR1<ADRS> Conversion operation Indeterminate ADCDR1,ADCDR2 ADCDR2<EOCF> INTADC interrupt request ADCDR1 ADCDR2 16.3.3 Register Setting 1. Set up the AD converter control register 1 (ADCCR1) as follows: ・ Choose the channel to AD convert using AD input channel ...
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Example :After selecting the conversion time 19.5 μ MHz and the analog input channel AIN3 pin, perform AD conversion once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH and store the ...
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Analog Input Voltage and AD Conversion Result 16.5 Analog Input Voltage and AD Conversion Result The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 16-4. 3FF H 3FE H ...
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... The internal equivalent circuit of the analog input pins is shown in Figure 16-5. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the output impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capacitor external to the chip. ...
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Precautions about AD Converter Page 172 TMP86FH92DMG ...
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Key-on Wakeup (KWU) TMP86FH92DMG have four pins P34 to P37, in addition to the P20 (INT5/STOP) pin, that can be used to exit STOP mode. When using these P34 to P37 pin’s input to exit STOP mode, pay attention ...
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Control 17.2 Control The P34 to P37 (STOP2 to STOP5) pins can individually be disabled/enabled using Key-on Wakeup Control Register (STOPCR).When these pins are used as a release input of STOP mode, beforehand they set to key-on wakeup by ...
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... The parallel PROM mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provided by the third party. High-speed access to the flash memory is available by controlling address and data signals directly. For the support of the program writer, please ask Toshiba sales represen- tative. ...
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Flash Memory Control 18.1 Flash Memory Control The flash memory is controlled via the flash memory control register (FLSCR) and flash memory standby control resister (FLSSTB). Flash Memory Control Register 7 6 FLSCR (0FFFH) Flash memory command sequence exe- ...
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RAM area.) 1. Transfer the control program of the FLSSTB register to the ...
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Command Sequence 18.2 Command Sequence The command sequence in the MCU and the serial PROM modes consists of six commands (JEDEC compatible), as shown in Table 18-1. Addresses specified in the command sequence are recognized with the lower 12 ...
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Chip Erase (All Erase) This command erases the entire flash memory in approximately 30 ms. The next command sequence cannot be executed until the erase operation is completed. To check the completion of the erase operation, perform read operations ...
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Toggle Bit (D6) 18.3 Toggle Bit (D6) After the byte program, chip erase, and security program command sequence is executed, any consecutive attempts to read from the same address is reversed bit 6 (D6) of the data (toggling between ...
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Access to the Flash Memory Area When the write, erase and security program are set in the flash memory, read and fetch operations cannot be performed in the entire flash memory area. Therefore, to perform these operations in the ...
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Access to the Flash Memory Area Example :After chip erasure, the program in the RAM area writes data 3FH to address F000H #### Flash Memory Chip erase Process #### ...
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Flash Memory Control in the MCU mode In the MCU mode, write operations are performed by executing the control program in the RAM area. Before execution of the control program, copy the control program into the RAM area or ...
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Access to the Flash Memory Area Example :After sector erasure (E000H-EFFFH), the program in the RAM area writes data 3FH to address E000H LDW #### Flash Memory Sector Erase Process #### LD ...
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Serial PROM Mode 19.1 Outline The TMP86FH92DMG has a 2048 byte BOOTROM (Mask ROM) for programming to flash memory. The BOOT- ROM is available in the serial PROM mode, and controlled by TEST, BOOT and RESET pins. Communication is ...
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Serial PROM Mode Setting 19.3 Serial PROM Mode Setting 19.3.1 Serial PROM Mode Control Pins To execute on-board programming, activate the serial PROM mode. Table 19-2 shows pin setting to activate the serial PROM mode. Note:The BOOT pin is ...