TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 153

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.2.2
14.2.3
(0028H)
(0029H)
SEDR
SESR
Note 1: The SEF flag is automatically set at completion of transfer. The SEF flag thus set is automatically cleared by reading the
Note 2: The WCOL flag is automatically set by a write to the SEDR register while transfer is in progress. Writing to the SEDR
Note 3: During master mode:
Note 4: Master mode:
is initiated by writing to this SEDR register. If the master device needs to write to the SEDR register after transfer
began, always check to see by means of an interrupt or by polling that the SEF flag (SESR<SEF>) is set, before
writing to the SEDR register.
The SEI Data Register (SEDR) is used to send and receive data. When the SEI is set for master, data transfer
SEI Status Register (SESR)
SEI Data Register (SEDR)
SED7
SEF
7
7
(2)
SESR register and accessing the SEDR register.
register during transfer has no effect. The WCOL flag thus set is automatically cleared by reading the SESR register and
accessing the SEDR register. No interrupts are generated for reasons that the WCOL flag is set.
This bit does not function; its data when read is “0”.
During slave mode:
The SOVF flag is automatically set when the device finishes reading the next data while the SEF flag is set. The SOVF
flag thus set is automatically cleared by reading the SESR register and accessing the SEDR register. The SOVF flag also
is cleared by a switchover to master mode. No interrupts are generated for reasons that the SOVF flag is set.
The MODF flag is set when the SS pin is driven low. At this time, the SEI performs the following operations:
1. Disables the SEI pin driver and sets the SCLK and MOSI pins as inputs in the high-impedance state.
2. Clears the SECR<MSTR> bit.
3. Forcefully clears the SECR<SEE> bit to disable the SEI system.
4. The MODF flag thus set is automatically cleared by a read of the SESR register and a write to the SECR register.
Slave mode:
This bit does not function; its data when read is 0.
WCOL
MODF
SOVF
SEF
SER bit has no effect. The maximum transfer rate is fc/4.
When the SEI is operating as a slave, the serial clock is input from the master and the setting of the
Note:Take note of the following relationship between the serial clock speed and fc on the master side:
Slave mode
WCOL
SED6
6
6
Transfer-finished flag (Note1)
Write collision error flag (Note2)
Overflow error flag (slave) (Note3)
Mode fault flow error flag (master) (Note4)
15.625 kbps < Transfer rate < fc/4 bps
Example) 15.625 kbps < Transfer rate < 4 Mbps (fc = 16 MHz at V
15.625 kbps < Transfer rate < 2 Mbps (fc = 8 MHz at V
SOVF
SED5
5
5
MODF
SED4
4
4
SED3
3
3
Page 139
SED2
2
2
0: Transfer in progress
1: Transfer completed
0: No write collision error occurred
1: Write collision error occurred
0: No overflow occurred
1: Overflow occurred
0: No mode fault occurred
1: Mode fault occurred
SED1
1
1
DD
SED0
= 2.7 to 5.5 V)
0
0
DD
(Initial value: 0000 ****)
R/W (Initial value: 0000 0000)
= 4.5 to 5.5 V)
TMP86FH92DMG
Read only