TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 172

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.6
Data Transfer of I
15.6.2
15.6.3
SCL pin
SDA pin
PIN
INTSBI
interrupt request
15.6.3.1
receiver mode, clear “0” to the MST, TRX and BB in SBICRB, set “1” to the PIN, “10” to the SBIM, and “00”
to bits SWRST1 and SWRST0.
address and the direction bit which are set to the SBIDBR are output. The time from generating the START
condition until the falling SCL pin takes t
The SCL pin is pulled-down to the low level while the PIN is “0”. When an interrupt request occurs, the TRX
changes by the hardware according to the direction bit only when an acknowledge signal is returned from the
slave device.
whether the mode is a master or slave.
2
C Bus
Note 1: Do not write a slave address to be output to the SBIDBR while data is transferred. If data is written to the
Note 2: The bus free must be confirmed by software within 98.0 μs (The shortest transmitting time according to the
After confirming that the serial bus interface pin is high level, for specifying the default setting to a slave
Confirm a bus free status (BB = 0).
Set the ACK to “1” and specify a slave address and a direction bit to be transmitted to the SBIDBR.
By writing “1” to the MST, TRX, BB and PIN, the start condition is generated on a bus and then, the slave
An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle, and the PIN is cleared to “0”.
Check the MST by the INTSBI interrupt process after an 1-word data transfer is completed, and determine
Start condition and slave address generation
1-word data transfer
Figure 15-9 Start Condition Generation and Slave Address Transfer
Note:The initialization of a serial bus interface circuit must be complete within the time from all devices which
(1)
Check the TRX and determine whether the mode is a transmitter or receiver.
When the MST is “1” (Master mode)
generate a stop condition (Described later) and terminate data transfer.
are connected to a bus have initialized to and device does not generate a start condition. If not, the data
can not be received correctly because the other device starts transferring before an end of the initiali-
zation of a serial bus interface circuit.
SBIDBR, data to been outputting may be destroyed.
I
"1" to the MST, TRX, BB, and PIN to generate the start conditions. If the writing of slave address and setting
of MST, TRX, BB and PIN doesn't finish within 98.0 μs, the other masters may start the transferring and the
slave address data written in SBIDBR may be broken.
2
C bus standard) after setting of the slave address to be output. Only when the bus free is confirmed, set
Test the LRB. When the LRB is “1”, a receiver does not request data. Implement the process to
When the TRX is “1” (Transmitter mode)
Start condition
A6
1
A5
2
LOW
A4
3
Slave address + Direction bit
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.
A3
4
A2
5
A1
6
A0
7
R/W
8
TMP86FH92DMG
9
Acknowledge
signal from a
slave device