TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 50

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.1
Interrupt latches (IL21 to IL2)
Example 1 :Clears interrupt latches
Example 2 :Reads interrupt latches
Example 3 :Tests interrupt latches
3.1
3.2
3.2.1
instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to accept
the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All
interrupt latches are initialized to “0” during reset.
"0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the
interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write
instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately
if interrupt is requested while such instructions are executed.
interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Non-
maskable interrupt is accepted regardless of the contents of the EIR.
registers are located on address 003AH, 003BH, and 0032H in SFR area, and they can be read and written by an
instructions (Including read-modify-write instructions such as bit manipulation or operation instructions).
Interrupt latches (IL21 to IL2)
Interrupt enable register (EIR)
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined
The interrupt latches are located on address 003CH, 003DH, and 003EH in SFR area. Each latch can be cleared to
Interrupt latches are not set to “1” by an instruction.
Since interrupt latches can be read, the status for interrupt requests can be monitored by software.
The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable
The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These
Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear
IMF = “0”, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable
flag (EF). By setting IMF to “1”, the interrupt becomes acceptable if the individuals are enabled. When an interrupt
is accepted, IMF is cleared to “0” after the latest status on IMF is stacked. Thus the maskable interrupts which
follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the
status before interrupt acceptance, is loaded on IMF again.
Interrupt master enable flag (IMF)
The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While
IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF
or IL (Enable interrupt by EI instruction)
In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally
on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or
IL should be executed before setting IMF="1".
DI
LDW
EI
LD
TEST
JR
(ILL), 1110100000111111B
WA, (ILL)
(ILL). 7
F, SSET
Page 36
; IMF← 0
; IL12, IL10 to IL6← 0
; IMF ← 1
; W ← ILH, A ← ILL
; if IL7 = 1 then jump
TMP86FH92DMG