TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 138

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.9
Status Flag
12.9
12.9.1
12.9.2
12.9.3
Status Flag
UART1SR<PERR> is set to “1”. The UART1SR<PERR> is cleared to “0” when the RD1BUF is read after
reading the UART1SR.
The UART1SR<FERR> is cleared to “0” when the RD1BUF is read after reading the UART1SR.
UART1SR<OERR> is set to “1”. In this case, the receive data is discarded; data in RD1BUF are not affected.
The UART1SR<OERR> is cleared to “0” when the RD1BUF is read after reading the UART1SR.
When parity determined using the receive data bits differs from the received parity bit, the parity error flag
When “0” is sampled as the stop bit in the receive data, framing error flag UART1SR<FERR> is set to “1”.
When all bits in the next data are received while unread data are still in RD1BUF, overrun error flag
RXD1 pin
UART1SR<FERR>
INTRXD1 interrupt
Shift register
Parity Error
Framing Error
Overrun Error
Shift register
RXD1 pin
UART1SR<PERR>
INTRXD1 interrupt
Figure 12-6 Generation of Framing Error
Figure 12-5 Generation of Parity Error
xxxx0 **
xxx0 **
Final bit
Parity
Page 124
pxxxx0
xxxx0
Stop
*
*
Stop
1pxxxx0
0xxxx0
After reading UART1SR then
RD1BUF clears FERR.
After reading UART1SR then
RD1BUF clears PERR.
TMP86FH92DMG