TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 84

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2
Watchdog Timer Control
Example :Setting the watchdog timer detection time to 2
8.2
8.2.1
timer is automatically enabled after the reset release.
Watchdog Timer Control
The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog
Within 3/4 of WDT
detection time
Within 3/4 of WDT
detection time
timer output is activated by the binary-counter overflow unless the binary counters are cleared. When
WDTCR1<WDTOUT> is set to “1” at this time, the reset request is generated and then internal hardware is
initialized. When WDTCR1<WDTOUT> is set to “0”, a watchdog timer interrupt (INTWDT) is generated.
mode, and automatically restarts (continues counting) when the STOP/IDLE/SLEEP mode is inactivated.
Malfunction Detection Methods Using the Watchdog Timer
The CPU malfunction is detected, as shown below.
If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog
The watchdog timer temporarily stops counting in the STOP mode including the warm-up or IDLE/SLEEP
Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code
1. Set the detection time, select the output, and clear the binary counter.
2. Clear the binary counter repeatedly within the specified detection time.
4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter
overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register,
may be 3/4 of the time set in WDTCR1<WDTT>. Therefore, write the clear code using a cycle shorter
than 3/4 of the time set to WDTCR1<WDTT>.
LD
LD
LD
:
:
LD
:
:
LD
(WDTCR2), 4EH
(WDTCR1), 00001101B
(WDTCR2), 4EH
(WDTCR2), 4EH
(WDTCR2), 4EH
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/fc [s], and resetting the CPU malfunction detection
: Clears the binary counters.
: WDTT ← 10, WDTOUT ← 1
: Clears the binary counters (always clears immediately before and
after changing WDTT).
: Clears the binary counters.
: Clears the binary counters.
TMP86FH92DMG