TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 27

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.3.3
internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.
(Either level-sensitive or edge-sensitive can be programmable selected) to the STOP pin. After the warm-up
period is completed, the execution resumes with the instruction which follows the STOP mode start instruc-
tion.
(4)
(5)
(6)
(7)
In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The
STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting
STOP mode
In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the
1st to 6th stages is also stopped.
however, on-chip peripherals remain active (Operate using the high-frequency clock and/or the low-
frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that
operation returns to NORMAL2 mode.
watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-
chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP
mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode. In SLOW1 and
SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th
stages is also stopped.
mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the high-frequency
clock.
enabled by setting “1” on bit SYSCR2<TGHALT>.
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.
SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF = “1”,
EF7 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt processing is
performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT interrupt latch
is set after returning to SLOW1 mode.
Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>.
In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are halted;
In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the
The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the SLEEP2
In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is
When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back again.
IDLE2 mode
SLEEP1 mode
SLEEP2 mode
SLEEP0 mode
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TMP86FH92DMG