TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 68

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TMP86C993XB

Manufacturer Part Number
TMP86C993XB
Description
EMULATION CHIP FOR TMP86F SSOP
Manufacturer
Toshiba
Datasheet

Specifications of TMP86C993XB

Accessory Type
Adapter
For Use With/related Products
TMP86F SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
5.2
P1 (P14 to P10) Port
5.2
and serial bus interface input/output. When using this port as divider output, UART2 output and serial bus interface
output, set the output latch to 1. When using this port as a port output, the output latch data(P1DR) is output to the P1
port.
spectively.
register.
P1OUTCR register’s corresponding bit to 0 after setting the P1DR to 1.
the pin status, read the P1PRD register.
P1 (P14 to P10) Port
The P1 port is a 5-bit input/output port shared with external interrupt input, divider output, UART2 input/output
When reset, the output latch (P1DR) and the push-pull control register(P1OUTCR) are initialized to 1 and 0,re-
The P1 allows its output circuit to be selected between N-channel open-drain or push-pull output by the P1OUTCR
The P1 port has programmable internal pull-up resistance to be controlled by P1PUCR.
When using this port as a port input, external interrupt input, UART2 input and serial bus interface input, set the
The P1 port has independent data input registers.To inspect the output latch status, read the P1DR register.To inspect
Data input (P1PRD)
Data output (P1DR)
Data input (P1DR)
P1OUTCRi input
Control output
Control input
P1OUTCRi
P1PUCRi
OUTEN
STOP
Output latch
D
D
Q
Q
Figure 5-3 P1 Port
Page 54
VDD
Note: i =
P1i
TMP86FH92DMG
4
to 0

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