KIT AVR/AVR32 DEBUGGER/PROGRMMR

ATAVRONEKIT

Manufacturer Part NumberATAVRONEKIT
DescriptionKIT AVR/AVR32 DEBUGGER/PROGRMMR
ManufacturerAtmel
SeriesAVR®
TypeDebugger
ATAVRONEKIT datasheets
 

Specifications of ATAVRONEKIT

ContentsProgrammer/DebuggerProcessor To Be EvaluatedAVR32
Data Bus Width32 bitInterface TypeISP, JTAG
Core ArchitectureAVRKit ContentsATAVRONEKIT
Tool / Board ApplicationsGeneral Purpose MCU, MPU, DSP, DSCDevelopment Tool TypeHardware / Software - Dev Kit (Dev Tool)
Rohs CompliantYesMcu Supported FamiliesAVR32 32-bit MCU
For Use With/related ProductsAVR® DevicesLead Free Status / RoHS StatusLead free / RoHS Compliant
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Features
High-performance, Low-power 8/16-bit
Non-Volatile Program and Data Memories
– 64K - 384K Bytes of In-System Self-Programmable Flash
– 4K - 8K Bytes Boot Section with Independent Lock Bits
– 2 KB - 4 KB EEPROM
– 4 KB - 32 KB Internal SRAM
External Bus Interface for up to 16M bytes SRAM
External Bus Interface for up to 128M bit SDRAM
Peripheral Features
– Four-channel DMA Controller with support for external requests
– Eight-channel Event System
– Eight 16-bit Timer/Counters
Four Timer/Counters with 4 Output Compare or Input Capture channels
Four Timer/Counters with 2 Output Compare or Input Capture channels
High-Resolution Extension on all Timer/Counters
Advanced Waveform Extension on two Timer/Counters
– Eight USARTs
IrDA modulation/demodulation for one USART
– Four Two-Wire Interfaces with dual address match (I
– Four SPI (Serial Peripheral Interface) peripherals
– AES and DES Crypto Engine
– 16-bit Real Time Counter with separate Oscillator
– Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters
– Two Two-channel, 12-bit, 1 Msps Digital to Analog Converters
– Four Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL and Prescaler
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interfaces
JTAG (IEEE 1149.1 Compliant) Interface for programming, test and debugging
PDI (Program and Debug Interface) for programming and debugging
I/O and Packages
– 78 Programmable I/O Lines
– 100 - lead TQFP
– 100 - ball CBGA
– 100 - ball VFBGA
Operating Voltage
– 1.6 – 3.6V
Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
Typical Applications
Industrial control
Climate control
Factory automation
ZigBee
Building control
Motor control
Board control
Networking
White Goods
Optical
®
®
TM
Atmel
AVR
XMEGA
Microcontroller
2
C and SMBus compatible)
Hand-held battery applications
Power tools
HVAC
Metering
Medical Applications
8/16-bit
XMEGA A1
Microcontroller
ATxmega384A1
ATxmega256A1
ATxmega192A1
ATxmega128A1
ATxmega64A1
Preliminary
8067M–AVR–09/10

ATAVRONEKIT Summary of contents

  • Page 1

    ... ZigBee • • Building control Motor control • • Board control Networking • • White Goods Optical ® ® TM Atmel AVR XMEGA Microcontroller 2 C and SMBus compatible) • Hand-held battery applications • Power tools • HVAC • Metering • Medical Applications ...

  • Page 2

    ... ATxmega64A1-C7U 64K + 4K Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For packaging information, see 100A 100-lead ...

  • Page 3

    Pinout/Block Diagram Figure 2-1. Block diagram and pinout INDEX CORNER 1 PA6 2 PA7 3 GND 4 AVCC 5 PB0 6 PB1 7 PB2 8 PB3 9 PB4 10 PB5 11 PB6 12 PB7 13 GND 14 VCC 15 ...

  • Page 4

    Figure 2-2. CBGA-pinout Top view Table 2-1. CBGA-pinout PK0 VCC B PK3 PK2 C VCC PK5 D GND PK6 E PQ0 ...

  • Page 5

    ... The Bootloader software in the Boot Flash section will continue to run while the Appli- cation Flash section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA power- ful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications ...

  • Page 6

    Block Diagram Figure 3-1. XMEGA A1 Block Diagram DACA PA[0..7] PORT A (8) ACA ADCA AREFA VCC/10 Int. Ref. Tempref AREFB ADCB ACB PB[0..7]/ PORT B (8) JTAG DACB IRCOM 8067M–AVR–09/10 PR[0..1] PQ[0..3] XTAL1 TOSC1 XTAL2 TOSC2 Oscillator Circuits/ ...

  • Page 7

    ... The XMEGA A application notes contain example code and show applied use of the modules and peripherals. The XMEGA A Manual and Application Notes are available from http://www.atmel.com/avr. 5. Disclaimer For devices that are not available yet, typical values contained in this datasheet are based on simulations and characterization of other AVR XMEGA microcontrollers manufactured on the same process technology ...

  • Page 8

    AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 138 instructions – Hardware multiplier • 32x8-bit registers directly connected to the ALU • Stack in SRAM • Stack Pointer accessible in I/O memory space • Direct ...

  • Page 9

    The program memory is In- System Self-Programmable Flash memory. 6.3 Register File The fast-access Register File contains 32 x 8-bit general purpose working registers with single clock cycle access time. ...

  • Page 10

    Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section ...

  • Page 11

    In-System Programmable Flash Program Memory The XMEGA A1 devices contain On-chip In-System Programmable Flash memory for program storage, see Flash address location is 16 bits. The Program Flash memory space is divided into Application and Boot sections. Both sections ...

  • Page 12

    Figure 7-2. Data Memory Map (Hexadecimal address) 2000 Internal SRAM (16 KB) 5FFF 6000 External Memory ( MB) FFFFFF 7.4.1 I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All ...

  • Page 13

    EBI - External Bus Interface • Supports SRAM up to – 512K Bytes using 2-port EBI – 16M Bytes using 3-port EBI • Supports SDRAM up to – 128M bit using 3-port EBI • Four software configurable Chip Selects ...

  • Page 14

    Production Signature Row The Production Signature Row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. The production signature row also contains a device ID that identify ...

  • Page 15

    Flash and EEPROM Page Size The Flash Program Memory and EEPROM data memory is organized in pages. The pages are word accessible for the Flash and byte accessible for the EEPROM. Table 7-2 on page 15 operations are performed ...

  • Page 16

    DMAC - Direct Memory Access Controller 8.1 Features • Allows High-speed data transfer – From memory to peripheral – From memory to memory – From peripheral to memory – From peripheral to peripheral • 4 Channels • From 1 ...

  • Page 17

    Event System 9.1 Features • Inter-peripheral communication and signalling with minimum latency • CPU and DMA independent operation • 8 Event Channels allows for signals to be routed at the same time • Events can be ...

  • Page 18

    Figure 9-1. The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Com- munication Module (IRCOM). Events can also be generated from software (CPU). All ...

  • Page 19

    System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator ...

  • Page 20

    Figure 10-1. Clock system overview Each clock source is briefly described in the following sub-sections. 10.3 Clock Options 10.3.1 32 kHz Ultra Low Power Internal Oscillator The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power ...

  • Page 21

    Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 10.3.4 0.4 ...

  • Page 22

    Power Management and Sleep Modes 11.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction registers to disable clocks to unused peripherals 11.2 Overview The XMEGA A1 provides various ...

  • Page 23

    System Control and Reset 12.1 Features • Multiple reset sources for safe operation and device reset – Power-On Reset – External Reset – Watchdog Reset – Brown-Out Reset – PDI reset – Software reset • Asynchronous reset – No ...

  • Page 24

    Software reset The MCU can be reset by the CPU writing to a special I/O register through a timed sequence. 12.4 WDT - Watchdog Timer 12.4.1 Features • 11 selectable timeout periods, from 8s. • Two ...

  • Page 25

    PMIC - Programmable Multi-level Interrupt Controller 13.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts ...

  • Page 26

    Table 13-1. Reset and Interrupt Vectors (Continued) Program Address (Base Address) Source 0x040 NVM_INT_base 0x044 PORTB_INT_base 0x048 ACB_INT_base 0x04E ADCB_INT_base 0x056 PORTE_INT_base 0x05A TWIE_INT_base 0x05E TCE0_INT_base 0x06A TCE1_INT_base 0x072 SPIE_INT_vect 0x074 USARTE0_INT_base 0x07A USARTE1_INT_base 0x080 PORTD_INT_base 0x084 PORTA_INT_base 0x088 ACA_INT_base ...

  • Page 27

    I/O Ports 14.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events – Sense both edges – ...

  • Page 28

    Push-pull Figure 14-1. I/O configuration - Totem-pole 14.3.2 Pull-down Figure 14-2. I/O configuration - Totem-pole with pull-down (on input) 14.3.3 Pull-up Figure 14-3. I/O configuration - Totem-pole with pull-up (on input) 14.3.4 Bus-keeper The bus-keeper’s weak output produces the ...

  • Page 29

    Figure 14-4. I/O configuration - Totem-pole with bus-keeper 14.3.5 Others Figure 14-5. Output configuration - Wired-OR with optional pull-down Figure 14-6. I/O configuration - Wired-AND with optional pull-up 8067M–AVR–09/10 DIRn OUTn INn OUTn INn INn OUTn XMEGA ...

  • Page 30

    Input sensing • Sense both edges • Sense rising edges • Sense falling edges • Sense low level Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure ...

  • Page 31

    T/C - 16-bit Timer/Counter 15.1 Features • Eight 16-bit Timer/Counters – Four Timer/Counters of type 0 – Four Timer/Counters of type 1 • Four Compare or Capture (CC) Channels in Timer/Counter 0 • Two Compare or Capture (CC) Channels ...

  • Page 32

    Figure 15-1. Overview of a Timer/Counter and closely related peripherals Timer/Counter Base Counter Timer Period Compare/Capture Channel B Compare/Capture Channel A Comparator The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is ...

  • Page 33

    AWEX - Advanced Waveform Extension 16.1 Features • Output with complementary output from each Capture channel • Four Dead Time Insertion (DTI) Units, one for each Capture channel • 8-bit DTI Resolution • Separate High and Low Side Dead-Time ...

  • Page 34

    Hi-Res - High Resolution Extension 17.1 Features • Increases Waveform Generator resolution by 2-bits (4x) • Supports Frequency, single- and dual-slope PWM operation • Supports the AWEX when this is enabled and used for the same Timer/Counter 17.2 Overview ...

  • Page 35

    RTC - 16-bit Real-Time Counter 18.1 Features • 16-bit Timer • Flexible Tick resolution ranging from 32.768 kHz • One Compare register • One Period register • Clear timer on Overflow or Compare Match • Overflow ...

  • Page 36

    TWI - Two-Wire Interface 19.1 Features • Four Identical TWI peripherals • Simple yet Powerful and Flexible Communication Interface • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space Allows ...

  • Page 37

    SPI - Serial Peripheral Interface 20.1 Features • Four Identical SPI peripherals • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of ...

  • Page 38

    USART 21.1 Features • Eight Identical USART peripherals • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High-resolution Arithmetic Baud Rate Generator • Supports Serial ...

  • Page 39

    IRCOM - IR Communication Module 22.1 Features • Pulse modulation/demodulation for infrared communication • Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed ...

  • Page 40

    Crypto Engine 23.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) Crypto module • DES Instruction – Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per 8-byte block • ...

  • Page 41

    ADC - 12-bit Analog to Digital Converter 24.1 Features • Two ADCs with 12-bit resolution • 2 Msps sample rate for each ADC • Signed and Unsigned conversions • 4 result registers with individual input channel control for each ...

  • Page 42

    Figure 24-1. ADC overview Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results ...

  • Page 43

    DAC - 12-bit Digital to Analog Converter 25.1 Features • Two DACs with 12-bit resolution • Msps conversion rate for each DAC • Flexible conversion range • Multiple trigger sources • 1 continuous output or 2 ...

  • Page 44

    AC - Analog Comparator 26.1 Features • Four Analog Comparators • Selectable Power vs. Speed • Selectable hysteresis – mV • Analog Comparator output available on pin • Flexible Input Selection – All pins on ...

  • Page 45

    Figure 26-1. Analog comparator overview Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled Pin inputs Internal inputs Pin inputs Internal inputs VCC scaled 8067M–AVR–09/10 XMEGA A1 + Pin 0 output AC0 - Interrupt sensitivity control + AC1 - ...

  • Page 46

    Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 26-1 on page ...

  • Page 47

    ... No limitation on debug/programming clock frequency versus system clock frequency 27.2 Overview The XMEGA A1 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s development tools - provides all the necessary functions to debug an application. It has support for program and data breakpoints, and can debug an application from C and high level language source code level, as well as assembler and disassembler level ...

  • Page 48

    ... The PDI physical interface uses one dedicated pin together with the Reset pin, and no general purpose pins are used. JTAG uses four general purpose pins on PORTB. The PDI is an Atmel proprietary protocol for communication between the microcontroller and Atmel’s or third party development tools. ...

  • Page 49

    Pinout and Pin Functions The pinout of XMEGA A1 is shown in I/O functionality, each pin may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate ...

  • Page 50

    RAS 2P 3P 29.1.5 Timer/Counter and AWEX functions OCnx OCnx OCnxLS OCnxHS 29.1.6 Communication functions SCL SDA SCLIN SCLOUT SDAIN SDAOUT XCKn RXDn TXDn SS MOSI MISO SCK 29.1.7 Oscillators, Clock and Event TOSCn XTALn CLKOUT EVOUT 29.1.8 Debug/System functions ...

  • Page 51

    TDI TDO TMS 29.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining ...

  • Page 52

    Table 29-3. Port C - Alternate functions PORT C PIN # INTERRUPT TCC0 GND 13 VCC 14 PC0 15 SYNC OC0A PC1 16 SYNC OC0B PC2 17 SYNC/ASYNC OC0C PC3 18 SYNC OC0D PC4 19 SYNC PC5 20 SYNC PC6 ...

  • Page 53

    Table 29-6. Port F - Alternate functions PORT F PIN # INTERRUPT TCF0 GND 43 VCC 44 PF0 45 SYNC OC0A PF1 46 SYNC OC0B PF2 47 SYNC/ASYNC OC0C PF3 48 SYNC OC0D PF4 49 SYNC PF5 50 SYNC PF6 ...

  • Page 54

    Table 29-9. Port K - Alternate functions PORT K PIN # INTERRUPT SDRAM 3P GND 73 VCC 74 PK0 75 SYNC PK1 76 SYNC PK2 77 SYNC/ASYNC PK3 78 SYNC PK4 79 SYNC PK5 80 SYNC PK6 81 SYNC PK7 ...

  • Page 55

    Table 29-12. ATxmega384/256/192/128/64A1 Boundary Scan Order Bit Number 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 ...

  • Page 56

    Bit Number ...

  • Page 57

    Bit Number 8067M–AVR–09/10 Signal Name PB3.Bidir PB3.Control PB2.Bidir PB2.Control PB1.Bidir ...

  • Page 58

    Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A1. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Table 30-1. Base Address ...

  • Page 59

    Base Address 0x09C0 0x0A00 0x0A40 0x0A80 0x0A90 0x0AA0 0x0AB0 0x0AC0 0x0B00 0x0B40 0x0B90 0x0BA0 0x0BB0 0x0BC0 8067M–AVR–09/10 Name Description SPID Serial Peripheral Interface on port D TCE0 Timer/Counter 0 on port E TCE1 Timer/Counter 1 on port E AWEXE Advanced ...

  • Page 60

    Instruction Set Summary Mnemonics Operands Description ADD Rd, Rr Add without Carry ADC Rd, Rr Add with Carry ADIW Rd, K Add Immediate to Word SUB Rd, Rr Subtract without Carry SUBI Rd, K Subtract Immediate SBC Rd, Rr ...

  • Page 61

    Mnemonics Operands Description CALL k call Subroutine RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare with Immediate SBRC Rr, b Skip if Bit in Register ...

  • Page 62

    Mnemonics Operands Description LD Rd, -Y Load Indirect and Pre-Decrement LDD Rd, Y+q Load Indirect with Displacement LD Rd, Z Load Indirect LD Rd, Z+ Load Indirect and Post-Increment LD Rd, -Z Load Indirect and Pre-Decrement LDD Rd, Z+q Load ...

  • Page 63

    Mnemonics Operands Description ROL Rd Rotate Left Through Carry ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear SBI A, b Set Bit in I/O Register ...

  • Page 64

    Packaging information 32.1 100A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions ...

  • Page 65

    D e 0.90 TYP 10 A 0.90 TYP 2325 Orchard Parkway San Jose, CA 95131 R 8067M–AVR–09/10 E Marked A1 Identifier TOP VIEW Øb A1 Corner 9 8 ...

  • Page 66

    ... A1 BALL BALL CORNER b Package Drawing Contact: packagedrawings@atmel.com 8067M–AVR–09/ TOP VIEW E1 100 - 0.35 ± 0.05 Ø BOTTOM VIEW TITLE 100C2, 100-ball ( Array), 0.65 mm Pitch, 7.0 x 7.0 x 1.0 mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) XMEGA A1 0. SIDE VIEW ...

  • Page 67

    Electrical Characteristics 33.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin with respect to Ground..-0. Maximum Operating Voltage ............................................ 3.6V DC Current per I/O Pin ............................................... 20.0 ...

  • Page 68

    Table 33-1. Current Consumption Symbol Parameter (2) Module current consumption RC32M RC32M w/DFLL RC2M RC2M w/DFLL RC32K PLL Watchdog normal mode BOD Continuous mode BOD Sampled mode Internal 1.00 V ref Temperature reference RTC with int. 32 kHz RC as ...

  • Page 69

    Speed Table 33-2. Symbol Clk The maximum CPU clock frequency of the XMEGA A1 devices is depending Figure 33-1 on page 69 Figure 33-1. Operating Frequency vs. Vcc 8067M–AVR–09/10 Operating voltage and frequency Parameter V CC ...

  • Page 70

    Flash and EEPROM Memory Characteristics Table 33-3. Endurance and Data Retention Symbol Parameter Flash EEPROM Table 33-4. Programming time Symbol Parameter Chip Erase Flash EEPROM Notes: 1. Programming is timed from the internal 2 MHz oscillator. 2. EEPROM is ...

  • Page 71

    ADC Characteristics Table 33-5. ADC Characteristics Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Gain Error Offset Error ADC ADC Clock frequency clk Conversion rate Conversion time (propagation delay) Sampling Time Conversion range AVCC Analog Supply Voltage ...

  • Page 72

    DAC Characteristics Table 33-7. DAC Characteristics Symbol Parameter INL Integral Non-Linearity DNL Differential Non-Linearity F Conversion rate clk AREF External reference voltage Reference input impedance Max output voltage Min output voltage Offset factory calibration accuracy Gain factory calibration accuracy ...

  • Page 73

    Brownout Detection Characteristics Table 33-10. Brownout Detection Characteristics Symbol Parameter BOD level 0 falling Vcc BOD level 1 falling Vcc BOD level 2 falling Vcc BOD level 3 falling Vcc BOD level 4 falling Vcc BOD level 5 falling ...

  • Page 74

    POR Characteristics Table 33-12. Power-on Reset Characteristics Symbol Parameter V POR threshold voltage falling Vcc POT- V POR threshold voltage rising Vcc POT+ 33.12 Reset Characteristics Table 33-13. Reset Characteristics Symbol Parameter Minimum reset pulse width Reset threshold voltage ...

  • Page 75

    Table 33-18. Maximum load capacitance (CL) and ESR recommendation for 32.768 kHz Crystal Crystal CL [pF] 6.5 9 Table 33-19. Device wake-up time from sleep Symbol Parameter Idle Sleep, Standby and Extended Standby sleep mode Power-save and Power-down Sleep mode ...

  • Page 76

    Typical Characteristics 34.1 Active Supply Current Figure 34-1. Active Supply Current vs. Frequency Figure 34-2. Active Supply Current vs. V 8067M–AVR–09/ MHz 25°C SYS 1. ...

  • Page 77

    Idle Supply Current Figure 34-3. Idle Supply Current vs. Frequency Figure 34-4. Active Supply Current vs. V 8067M–AVR–09/ MHz 25°C SYS 1.8V 1 ...

  • Page 78

    Power-down Supply Current Figure 34-5. Power-down Supply Current vs. Temperature 34.4 Power-save Supply Current Figure 34-6. Power-save Supply Current vs. Temperature 8067M–AVR–09/10 2.5 2 1.5 1 0.5 0 -40 -30 -20 - Temperature [°C] Sampled BOD, WDT, ...

  • Page 79

    Pin Pull-up Figure 34-7. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage Figure 34-8. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage 8067M–AVR–09/ 1.8V CC 100 0.2 0.4 0.6 ...

  • Page 80

    Figure 34-9. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage 34.6 Pin Thresholds and Hysteresis Figure 34-10. I/O Pin Input Threshold Voltage vs. V 8067M–AVR–09/ 3.3V CC 180 160 140 120 100 80 85 ° ...

  • Page 81

    Figure 34-11. I/O Pin Input Threshold Voltage vs. V Figure 34-12. I/O Pin Input Hysteresis vs. V 8067M–AVR–09/ I/O Pin Read as “0” IL 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 ...

  • Page 82

    Figure 34-13. Reset Input Threshold Voltage vs. V Figure 34-14. Reset Input Threshold Voltage vs. V 8067M–AVR–09/ I/O Pin Read as “1” IH 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.6 1.8 2 2.2 2.4 ...

  • Page 83

    Bod Thresholds Figure 34-15. BOD Thresholds vs. Temperature Figure 34-16. BOD Thresholds vs. Temperature 8067M–AVR–09/10 BOD Level = 1.6V 1.638 1.632 1.626 1.62 1.614 1.608 1.602 -40 -30 -20 - Temperature [°C] BOD Level = 2.9V 3.01 ...

  • Page 84

    Bandgap Figure 34-17. Internal 1.00V Reference vs. Temperature. 34.9 Analog Comparator Figure 34-18. Analog Comparator Hysteresis vs. V 8067M–AVR–09/10 1.004 1.0035 1.003 1.0025 1.002 1.0015 1.001 1.0005 1 0.9995 0.999 -40 -30 -20 - High-speed, Small hysteresis ...

  • Page 85

    Figure 34-19. Analog Comparator Hysteresis vs. V Figure 34-20. Analog Comparator Propagation Delay vs. V 8067M–AVR–09/10 Large hysteresis 1.6 1.8 2 2.2 2.4 High-speed 120 100 1.6 1.8 ...

  • Page 86

    Oscillators and Wake-up Time Figure 34-21. Internal 32.768 kHz Oscillator Frequency vs. Temperature Figure 34-22. Ultra Low-Power (ULP) Oscillator Frequency vs. Temperature 8067M–AVR–09/10 1.024 kHz output 1.03 1.025 1.02 1.015 1.01 1.005 1 0.995 0.99 -40 -30 -20 -10 ...

  • Page 87

    Figure 34-23. Internal 2 MHz Oscillator CalA Calibration Step Size Figure 34-24. Internal 2 MHz Oscillator CalB Calibration Step Size 8067M–AVR–09/10 ° - 0.006 0.005 0.004 0.003 0.002 0.001 0 0 ...

  • Page 88

    Figure 34-25. Internal 32 MHz Oscillator CalA Calibration Step Size Figure 34-26. Internal 32 MHz Oscillator CalB Calibration Step Size 8067M–AVR–09/10 ° - 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 ...

  • Page 89

    PDI Speed Figure 34-27. PDI Speed vs. V 8067M–AVR–09/ 1.6 1.8 2 2.2 2.4 XMEGA A1 2.6 2.8 3 3.2 3 °C 3.6 89 ...

  • Page 90

    Errata 35.1 ATxmega128A1 rev. H • Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously • VCC voltage scaler for AC is non-linear • The ADC has up to ±2 LSB inaccuracy ...

  • Page 91

    Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator ...

  • Page 92

    Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2 order to get a cor- rect result, or keep ADC voltage reference below 2 Sampling ...

  • Page 93

    Increased noise when using internal 1.0V reference at low temperature When operating at below 0°C and using internal 1.0V reference the RMS noise will LSB, Peak-to-peak noise LSB. Problem fix/Workaround Use averaging to ...

  • Page 94

    DAC has up to ±10 LSB noise in Sampled Mode The DAC has noise ±10 LSB in Sampled Mode for entire operation range. Problem fix/Workaround Use the DAC in continuous mode. 17. DAC is nonlinear and ...

  • Page 95

    EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/Workaround Before writing to NVM DATA0, for example when doing ...

  • Page 96

    Flash Power Reduction Mode can not be enabled when entering sleep If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby sleep mode, the device will only wake up on every fourth wake-up request. If Flash ...

  • Page 97

    If EBI Power Reduction Bit is set while EBI is enabled, accessing external memory could result in bus hang-up, blocking all further access to all data memory. Problem fix/Workaround Ensure that EBI is disabled before setting EBI Power Reduction bit. ...

  • Page 98

    Problem fix/Workaround Clear the flag in software after address interrupt. 39. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag ...

  • Page 99

    WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/Workaround Wait ...

  • Page 100

    ATxmega128A1 rev. G • Bootloader Section in Flash is non-functional • Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously • DAC is nonlinear and inaccurate when reference is above 2.4V • ADC ...

  • Page 101

    ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the ...

  • Page 102

    EEPROM erase and write does not work with all System Clock sources When doing EEPROM erase or Write operations with other clock sources than the 2 MHz RCOSC, Flash will be read wrongly for one or two clock cycles ...

  • Page 103

    JTAG enable does not override Analog Comparator B output When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT on pin 7 if this is enabled. Problem fix/Workaround AC0OUT for ACB should not be enabled ...

  • Page 104

    Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 36.1 8067M – 09/10 1. 36.2 8067L – 08/10 ...

  • Page 105

    36.5 8067I – 04/ 36.6 8067H – 04/ 36.7 8067G – 11/ 36.8 8067F – 09/ 8067M–AVR–09/10 ...

  • Page 106

    36.9 8067E – 08/ 36.10 8067D – 07/ 36.11 8067C – 06/ 36.12 8067B – 05/ 10. 11. 12. ...

  • Page 107

    Updated Figure 6-1 on page 8. Inserted a new Figure 15-1 on page 32. Updated Speed grades in “Speed” on page Added a new ATxmega384A1 device in page ...

  • Page 108

    Table of Contents Features ..................................................................................................... 1 Typical Applications ................................................................................ 1 1 Ordering Information ............................................................................... 2 2 Pinout/Block Diagram .............................................................................. 3 3 Overview ................................................................................................... 5 4 Resources ................................................................................................. 7 5 Disclaimer ................................................................................................. 7 6 AVR CPU ................................................................................................... 8 7 Memories ................................................................................................ ...

  • Page 109

    Power Management and Sleep Modes ................................................. 22 12 System Control and Reset .................................................................... 23 13 PMIC - Programmable Multi-level Interrupt Controller ....................... 25 14 I/O Ports .................................................................................................. 27 15 T/C - 16-bit Timer/Counter ..................................................................... 31 16 AWEX - Advanced ...

  • Page 110

    TWI - Two-Wire Interface ....................................................................... 36 20 SPI - Serial Peripheral Interface ............................................................ 37 21 USART ..................................................................................................... 38 22 IRCOM - IR Communication Module .................................................... 39 23 Crypto Engine ........................................................................................ 40 24 ADC - 12-bit Analog to Digital Converter ...

  • Page 111

    Pinout and Pin Functions ...................................................................... 49 30 Peripheral Module Address Map .......................................................... 58 31 Instruction Set Summary ...................................................................... 60 32 Packaging information .......................................................................... 64 33 Electrical Characteristics ...................................................................... 67 34 Typical Characteristics .......................................................................... 76 8067M–AVR–09/10 28.3 IEEE 1149.1 (JTAG) ...

  • Page 112

    Errata ....................................................................................................... 90 36 Datasheet Revision History ................................................................ 104 Table of Contents....................................................................................... i 8067M–AVR–09/10 34.10 Oscillators and Wake-up Time ........................................................................86 34.11 PDI Speed .......................................................................................................89 35.1 ATxmega128A1 rev. H ....................................................................................90 35.2 ATxmega128A1 rev. G ..................................................................................100 36.1 8067M – 09/10 ...............................................................................................104 ...

  • Page 113

    ... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...