LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 196
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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5. Pin description
6. Register description
UM10237_4
User manual
Table 157. GPIO pin description
LPC2400 has up to five 32-bit General Purpose I/O ports. PORT0 and PORT1 are
controlled via two groups of registers as shown in
from them, LPC2400 can have three additional 32-bit ports, PORT2, PORT3 and PORT4.
Details on a specific GPIO port usage can be found in the chapters "Pin Configuration"
and "Pin Connect Block".
Legacy registers shown in
devices, using existing code. The functions and relative timing of older GPIO
implementations is preserved. Only PORT0 and PORT1 can be controlled via the legacy
port registers.
The registers in
the LPC2400’s GPIO ports. These registers are located directly on the local bus of the
CPU for the fastest possible read and write timing. They can be accessed as byte or
half-word long data, too. A mask register allows access to a group of bits in a single GPIO
port independently from other bits in the same port.
When PORT0 and PORT1 are used, user must select whether these ports will be
accessed via registers that provide enhanced features or a legacy set of registers (see
Section 3–3.4 “Other system controls and status flags” on page
fast and legacy GPIO registers are controlling the same physical pins, these two port
control branches are mutually exclusive and operate independently. For example,
changing a pin’s output via a fast register will not be observable via the corresponding
legacy register.
The following text will refer to the legacy GPIO as "the slow" GPIO, while GPIO equipped
with the enhanced features will be referred as "the fast" GPIO.
Pin Name
P0[31:0]
P1[31:0]
P2[31:0]
P3[31:0]
P4[31:0]
Type
Input/
Output
Table 10–159
Rev. 04 — 26 August 2009
Description
General purpose input/output. These are typically shared with other
peripherals functions and will therefore not all be available in an
application. Packaging options may affect the number of GPIOs
available in a particular device.
Some pins may be limited by requirements of the alternate functions of
the pin. For example, the pins containing the I
open-drain for any function selected on that pin. Details may be found
in the LPC2400 pin description in
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
Table 10–158
represent the enhanced GPIO features available on all of
allow backward compatibility with earlier family
Table 10–158
Section
8–4.
38). While both of a port’s
and
2
C0 functions are
Table
UM10237
© NXP B.V. 2009. All rights reserved.
10–159. Apart
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