LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 772
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Table 656.Interrupt Error Status register
Table 657.Interrupt Error Clear register (DMACIntErrClr -
Table 658.Raw Interrupt Terminal Count Status register
Table 659.Raw Error Interrupt Status register
Table 660.Enabled Channel register (DMACEnbldChns -
Table 661.Software Burst Request register (DMACSoftBReq
Table 662.Software Single Request register
Table 663.Software Last Burst Request register
Table 664.Software Last Single Request register
Table 665.Configuration register (DMACConfiguration -
Table 666.Synchronization register (DMACSync - address
Table 667.Channel Source Address registers
Table 668.Channel Destination Address registers
Table 669.Channel Linked List Item registers (DMACC0LLI -
Table 670.Channel Control registers (DMACC0Control -
Table 671.Source or destination burst size . . . . . . . . . . .729
Table 672.Source or destination transfer width . . . . . . . .730
Table 673.Protection bits . . . . . . . . . . . . . . . . . . . . . . . . .730
Table 674.Channel Configuration registers
Table 675.Flow control and transfer type bits . . . . . . . . .733
Table 676.DMA request signal usage . . . . . . . . . . . . . . .737
Table 677.EmbeddedICE pin description . . . . . . . . . . . .741
Table 678.EmbeddedICE logic registers . . . . . . . . . . . . .742
Table 679.ETM configuration . . . . . . . . . . . . . . . . . . . . .744
Table 680.ETM pin description . . . . . . . . . . . . . . . . . . . .745
Table 681.ETM Registers . . . . . . . . . . . . . . . . . . . . . . . .746
Table 682.RealMonitor stack requirement. . . . . . . . . . . .751
UM10237_4
User manual
description . . . . . . . . . . . . . . . . . . . . . . . . . . .722
(DMACIntErrorStatus - address 0xFFE0 400C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .723
address 0xFFE0 4010) bit description . . . . . .723
(DMACRawIntTCStatus - address 0xFFE0 4014)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .723
(DMACRawIntErrorStatus - address
0xFFE0 4018) bit description . . . . . . . . . . . . .724
address 0xFFE0 401C) bit description . . . . . .724
- address 0xFFE0 4020) bit description . . . . .724
(DMACSoftSReq - address 0xFFE0 4024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .725
(DMACSoftLBReq - address 0xFFE0 4028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .725
(DMACSoftLSReq - address 0xFFE0 402C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .726
address 0xFFE0 4030) bit description . . . . . .726
0xFFE0 4034) bit description . . . . . . . . . . . . .726
(DMACC0SrcAddr - address 0xFFE0 4100 and
DMACC1SrcAddr - address 0xFFE0 4120) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .727
(DMACC0DestAddr - address 0xFFE0 4104 and
DMACC1DestAddr - address 0xFFE0 4124) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .728
address 0xFFE0 4108 and DMACC1LLI - address
0xFFE0 4128) bit description . . . . . . . . . . . . .728
address 0xFFE0 410C and DMACC1Control -
address 0xFFE0 412C) bit description . . . . . .729
(DMACC0Configuration - address 0xFFE0 4110
and DMACC1Configuration - address
0xFFE0 4130) bit description . . . . . . . . . . . . .731
Rev. 04 — 26 August 2009
Table 683.Acronyms and abbreviations . . . . . . . . . . . . . 759
Chapter 36: LPC24XX Supplementary information
UM10237
© NXP B.V. 2009. All rights reserved.
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