LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 71
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
5.2.1 Memory transaction endianness
5.2.2 Memory transaction size
5.2.3 Write protected memory areas
5.4.1 Write buffers
5.2 AHB slave memory interface
5.3 Pad interface
5.4 Data buffers
The AHB slave memory interface allows access to external memories.
The endianness of the data transfers to and from the external memories is determined by
the Endian mode (N) bit in the EMCConfig register.
Note: The memory controller must be idle (see the busy field of the EMCStatus Register)
before endianness is changed, so that the data is transferred correctly.
Memory transactions can be 8, 16, or 32 bits wide. Any access attempted with a size
greater than a word (32 bits) causes an ERROR response to the AHB bus and the transfer
is terminated.
Write transactions to write-protected memory areas generate an ERROR response to the
AHB bus and the transfer is terminated.
The pad interface block provides the interface to the pads. The pad interface uses
feedback clocks, FBCLKIN[3:0], to resynchronize SDRAM read data from the off-chip to
on-chip domains.
The AHB interface reads and writes via buffers to improve memory bandwidth and reduce
transaction latency. The EMC contains four 16-word buffers. The buffers can be used as
read buffers, write buffers, or a combination of both. The buffers are allocated
automatically.
The buffers must be disabled during SDRAM and SyncFlash initialization. They must also
be disabled when performing SyncFlash commands. The buffers must be enabled during
normal operation.
The buffers can be enabled or disabled for static memory using the EMCStaticConfig
Registers.
Write buffers are used to:
Write buffer operation:
•
•
Merge write transactions so that the number of external transactions are minimized.
Buffer data until the EMC can complete the write transaction, improving AHB write
latency.
Convert all dynamic memory write transactions into quadword bursts on the external
memory interface. This enhances transfer efficiency for dynamic memory.
Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Rev. 04 — 26 August 2009
Chapter 5: LPC24XX External Memory Controller (EMC)
UM10237
© NXP B.V. 2009. All rights reserved.
71 of 792
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