LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 714
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
Fig 145. GPDMA in the LPC24XX
EXTERNAL
MEMORY
4.2.4 Channel Logic and Channel Register Bank
4.2.5 Interrupt Request
4.2.6 AHB Master Interface
4.2.7 Bus and transfer widths
4.2.8 Endian behavior
The channel logic and channel register bank contains registers and logic required for each
DMA channel.
The interrupt request generates interrupts to the ARM processor.
The GPDMA contains a full AHB master. See
connected in the LPC24XX.
The AHB master is capable of dealing with all types of AHB transactions, including:
The physical width of the AHB bus is 32 bits. Source and destination transfers can be of
differing widths, and can be the same width or narrower than the physical bus width. The
GPDMA packs or unpacks data as appropriate.
The GPDMA can cope with both little-endian and big-endian addressing. You can set the
endianness of each AHB master individually.
Internally the GPDMA treats all data as a stream of bytes instead of 16 bit or 32 bit
quantities. This means that when performing mixed-endian activity, where the endianness
of the source and destination are different, byte swapping of the data within the 32 bit data
bus is observed.
Note: If you do not require byte swapping then avoid using different endianness between
the source and destination addresses.
CONTROLLER
EXTERNAL
•
•
•
MEMORY
Split, retry, and error responses from slaves. If a peripheral performs a split or retry,
the GPDMA stalls and waits until the transaction can complete.
Locked transfers for source and destination of each stream.
Setting of protection bits for transfers on each stream.
BRIDGE
ARM7
AHB
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Rev. 04 — 26 August 2009
AHB1
SLAVE
AHB
GPDMA
SRAM
16 kB
MASTER
AHB
Figure 32–145
BRIDGE
APB
for how the GPDMA is
UM10237
SD/MMC
© NXP B.V. 2009. All rights reserved.
SSP1
SSP0
I2S1
I2S0
714 of 792
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