ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 100

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

ST92F124/F150/F250 - INTERRUPTS
5.6 EXTERNAL INTERRUPTS
The ST9 core contains 8 external interrupt sources
grouped into four pairs.
Table 19. External Interrupt Channel Grouping
Each source has a trigger control bit TEA0,..TED1
(R242,EITR.0,..,7 Page 0) to select triggering on
the rising or falling edge of the external pin. If the
Trigger control bit is set to “1”, the corresponding
pending bit IPA0,..,IPD1 (R243,EIPR.0,..,7 Page
0) is set on the input pin rising edge, if it is cleared,
the pending bit is set on the falling edge of the in-
put pin. Each source can be individually masked
through
IMA0,..,IMD1 (EIMR.7,..,0). See
Figure 50. Priority Level Examples
The priority level of the external interrupt sources
can be programmed among the eight priority lev-
els with the control register EIPLR (R245). The pri-
ority level of each pair is software defined using
the bits PRL2,PRL1. For each pair, the even chan-
nel (A0,B0,C0,D0) of the group has the even prior-
ity level and the odd channel (A1,B1,C1,D1) has
the odd (lower) priority level.
Figure 50
100/429
9
INT.C1: 001=1
SOURCE
INT.D0:
INT.D1:
INT.C0: 000=0
WKUP[0:15]
Interrupt
External
INT6
INT5
INT4
INT3
INT2
INT1
INT0
101=5
100=4
PRIORITY
shows an example of priority levels.
the
PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A
1
Channel
0
INTD0
INTC1
INTC0
INTD1
INTB1
INTB0
INTA1
INTA0
corresponding
0
0
P6[7,5] P5[7:5, 2:0] P4[7,4]
1
0
P8[1:0] P7[7:5]
I/O Port Pin
0
Figure
P6.1
P6.3
P6.2
P6.3
P6.2
P6.0
P6.0
1
SOURCE
control
INT.A0: 010=2
INT.A1: 011=3
INT.B1: 101=5
INT.B0: 100=4
EIPLR
51.
PRIORITY
bit
Figure 51
ternal interrupts and vectors.
Table 20. Multiplexed Interrupt Sources
– The source of INTA0 can be selected between
– The source of INTA1 can be selected between
– The source of INTB0 can be selected between
– The source of INTB1 can be selected between
– The source of INTC0 can be selected between
– The source of INTC1 can be selected between
– The source of INTD0 can be selected between
– The source of INTD1 can be selected between
Warning: When using external interrupt channels
shared by both external interrupts and peripherals,
special care must be taken to configure control
registers both for peripheral and interrupts.
Channel
the external pin INT0 or the Timer/Watchdog pe-
ripheral using the IA0S bit in the EIVR register
(R246 Page 0).
the external pin INT1 or the Standard Timer us-
ing the INTS bit in the STC register (R232 Page
11).
the external pin INT2 or the on-chip Extended
Function Timer 0 using the EFTIS bit in the CR3
register (R255 Page 28).
external pin INT3 or the on-chip Extended Func-
tion Timer 1 using the EFTIS bit in the CR3 reg-
ister (R255 Page 29).
external pin INT4 or the On-chip E
Memory using bit FEIEN in the ECR register (Ad-
dress 224001h).
external pin INT5 or the on-chip SPI using the
SPIS bit in the SPCR0 register (R241 Page 7).
external pin INT6 or the Reset and Clock Unit
RCCU using the INT_SEL bit in the CLKCTL reg-
ister (R240 Page 55).
the NMI pin and the WUIMU Wakeup/Interrupt
Lines using the ID1S bit in the WUCRTL register
(R248 Page 9).
INTC0
INTC1
INTD0
INTD1
INTA0
INTA1
INTB0
INTB1
and
Wake-up Management Unit
Extended Function Timer 0
Extended Function Timer 1
Internal Interrupt Source
Table 20
Timer/Watchdog
Standard Timer
SPI Interrupt
E
3 TM
RCCU
give an overview of the ex-
/Flash
3 TM
/Flash
Interrupt
External
INT0
INT1
INT2
INT3
INT4
INT5
INT6