ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 99

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

ARBITRATION MODES (Cont’d)
End of Interrupt Routine
The iret Interrupt Return instruction executes
the following steps:
– The Flag register is popped from system stack.
– If ENCSR is set, CSR is popped from system
– The PC high byte is popped from system stack.
– The PC low byte is popped from system stack.
– All unmasked Interrupts are enabled by setting
– The priority level of the interrupted routine is
Figure 49. Complex Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN set to 1 during the interrupt routine execution
Priority Level of
Interrupt Request
0
1
2
3
4
5
6
7
stack.
the CICR.IEN bit.
popped from the special register (NICR) and
copied into CPL.
CPL is set to 7
INT5
MAIN
ei
CPL=5
INT 5
INT2
INT3
INT4
ei
CPL=2
INT0
INT 2
ei
CPL2 < CPL4:
Serviced just after ei
CPL=0
INT 0
CPL=2
INT 2
ei
CPL6 > CPL3:
INT6 pending
CPL=3
INT 3
INT6
CPL=4
INT 4
INT2
ei
– If ENCSR is reset, CSR is used instead of ISR,
The suspended routine thus resumes at the inter-
rupted instruction.
Figure 48
if the ei instruction is not used in the interrupt
service routines, nested and concurrent modes
are equivalent.
Figure 49
showing how nested mode allows nested interrupt
processing (enabled inside the interrupt service
routinesi using the ei instruction) according to
their priority level.
CPL=2
INT 2
unless the program returns to another nested
routine.
ST92F124/F150/F250 - INTERRUPTS
CPL=4
INT 4
contains a simple example, showing that
contains a more complex example
CPL=5
INT 5
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
CPL=6
INT 6
CPL=7
MAIN
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