ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 117

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

WAKE-UP / INTERRUPT LINES MANAGEMENT UNIT (Cont’d)
5.12.4 Programming Considerations
The following paragraphs give some guidelines for
designing an application program.
5.12.4.1 Procedure for Entering/Exiting STOP
mode
1. Program the polarity of the trigger event of
2. Check that at least one mask bit (registers
3. Reset at least the unmasked pending bits: this
4. Set the ID1S bit in the WUCTRL register and
5. To generate an interrupt on channel INTD1, bits
6. Reset the STOP bit in register WUCTRL and
7. To enter STOP mode, write the sequence 1, 0,
8. The code to be executed just after the STOP
external wake-up lines by writing registers
WUTRH and WUTRL.
WUMRH, WUMRL) is equal to 1 (so at least
one external wake-up line is not masked).
allows a rising edge to be generated on the
INTD1 channel when the trigger event occurs
(an interrupt on channel INTD1 is recognized
when a rising edge occurs).
set the WKUP-INT bit.
EITR.1 (R242.7, Page 0) and EIMR.1 (R244.7,
Page 0) must be set and bit EIPR.7 must be
reset. Bits 7 and 6 of register R245, Page 0
must be written with the desired priority level for
interrupt channel INTD1.
the EX_STP bit in the CLK_FLAG register
(R242.7, Page 55). Refer to the RCCU chapter.
1 to the STOP bit in the WUCTRL register with
three consecutive write operations.
sequence must check the status of the STOP
and RCCU EX_STP bits to determine if the ST9
entered STOP mode or not (See “Wake-up
Mode Selection” on page 114. for details). If the
ST9 did not enter in STOP mode it is necessary
to reloop the procedure from the beginning, oth-
erwise the procedure continues from next point.
9. Poll the wake-up pending bits to determine
10.Clear the wake-up pending bit that was set.
5.12.4.2 Simultaneous Setting of Pending Bits
It is possible that several simultaneous events set
different pending bits. In order to accept subse-
quent events on external wake-up/interrupt lines, it
is necessary to clear at least one pending bit: this
operation allows a rising edge to be generated on
the INTD1 line (if there is at least one more pend-
ing bit set and not masked) and so to set EIPR.7
bit again. A further interrupt on channel INTD1 will
be serviced depending on the status of bit EIMR.7.
Two possible situations may arise:
1. The user chooses to reset all pending bits: no
2. The user chooses to keep at least one pending
which wake-up line caused the exit from STOP
mode.
further interrupt requests will be generated on
channel INTD1. In this case the user has to:
– Reset EIMR.7 bit (to avoid generating a spuri-
– Reset WUPRH register using a read-modify-
– Clear the EIPR.7 bit
– Reset the WUPRL register using a read-mod-
bit active: at least one additional interrupt
request will be generated on the INTD1 chan-
nel. In this case the user has to reset the
desired pending bits with a read-modify-write
instruction (AND, BRES, BAND). This operation
will generate a rising edge on the INTD1 chan-
nel and the EIPR.7 bit will be set again. An
interrupt on the INTD1 channel will be serviced
depending on the status of EIMR.7 bit.
ous interrupt request during the next reset op-
eration on the WUPRH register)
write instruction (AND, BRES, BAND)
ify-write instruction (AND, BRES, BAND)
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