ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 411

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

KNOWN LIMITATIONS (Cont’d)
13.3 I2C LIMITATIONS
13.3.1 Start condition ignored in multimaster mode
Description
In multimaster configurations, if the ST9 I2C re-
ceives a START condition from another I2C
master after the START bit is set in the I2CCR reg-
ister and before the START condition is generated
by the ST9 I2C, it may ignore the START condition
from the other I2C master. In this case, the ST9
master will receive a NACK from the other device.
Workaround
On reception of the NACK, ST9 can send a re-start
and Slave address to re-initiate communication.
13.3.2 Missing BUS error in master transmitter
mode
Description
BERR will not be set if an error is detected during
the first or second pulse of each 9-bit transaction.
Single Master Mode:
If a Start or Stop is issued during the first or
second pulse of a 9-bit transaction, the BERR flag
will not be set and transfer will continue however
the BUSY flag will be reset.
Section 13.3.1
Section 13.3.2
Section 13.3.3
Section 13.3.4
Section 13.3.5
Section 13.3.6
Limitations
Start condition ignored
Missing bus error
AF bit (acknowledge failure flag)
BUSY bit
ARLO (arbitration lost)
BUSY flag
Description
ST92F124/F150/F250 - KNOWN LIMITATIONS
Multimaster Mode:
Normally the BERR bit would be set whenever un-
authorized transmission takes place while transfer
is already in progress. However, an issue will arise
if an external master generates an unauthorized
Start or Stop while the I2C master is on the first or
second pulse of a 9-bit transaction.
Workaround
Single Master Mode:
Slave devices should issue a NACK when they re-
ceive a misplaced Start or Stop. The reception of a
NACK or BUSY by the master in the middle of
communication gives the possibility to reinitiate
transmission.
Multimaster Mode:
It is possible to work around the problem by polling
the BUSY bit during I2C master mode transmis-
sion. The resetting of the BUSY bit can then be
handled in a similar manner as the BERR flag
being set.
Mustimaster mode
Master transmitter mode
Transmitter mode (Master and Slave)
Mustimaster mode
Multimaster mode
All
Mode
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