ST92F150CV1TB STMicroelectronics, ST92F150CV1TB Datasheet - Page 315

• Manufacturer Part Number: ST92F150CV1TB
• Description: MCU 8BIT 128K FLASH 100TQFP
• Manufacturer: STMicroelectronics
• Series: ST9r

Specifications of ST92F150CV1TB

• Core Processor: ST9
• Core Size: 8/16-Bit
• Speed: 24MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SCI, SPI
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ST92F15x
• Core: ST9
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 24 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST92F150-EPB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit x 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4883

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Bit 5 = RDOF Receiver Data Overflow
The RDOF gets set to a logic one if the data in the
RXDATA register has not been read and new data
is ready to be transferred to the RXDATA register.
The old RXDATA information is lost since it is
overwritten with new data.
RDOF is cleared by reading the ERROR register
with RDOF set, while the CONTROL.JE bit is reset
or while the CONTROL.JDIS bit is set, or on reset.
0: No receiver data overflow condition occurred
1: Receiver data overflow condition occurred
Bit 4 = TRA Transmit Request Aborted
The TRA gets set to a logic one if a transmit op-
code is aborted by the JBLPD state machine.
Many conditions may cause a TRA. They are ex-
plained in the transmit opcode section. If the TRA
bit gets set after a TXOP write, then a transmit is
not attempted, and the TRDY bit is not cleared.
If a TRA error condition occurs, then the requested
transmit is aborted, and the JBLPD peripheral
takes appropriate measures as described under
the TXOP register section.
TRA is cleared on reset, while the CONTROL.JE
bit is reset or while the CONTROL.JDIS bit is set.
0: No transmission request aborted
1: Transmission request aborted
Bit 3 = RBRK Received Break Symbol Flag
The RBRK gets set to a logic one if a valid break
(BRK) symbol is detected from the filtered VPWI
pin. A Break received from the J1850 bus will can-
cel queued transmits of all types. The RBRK bit re-
mains set as long as the break character is detect-
ed from the VPWI. Reads of the ERROR register
will not clear the RBRK bit as long as a break char-
acter is being received. Once the break character
is gone, a final read of the ERROR register clears
this bit.
An RBRK error occurs once for a frame if it is re-
ceived during a frame. Afterwards, the receiver is
disabled from receiving information (other than the
break) until an EOFM symbol is received.
RBRK bit is cleared on reset, while the CON-
TROL.JE bit is reset or while the CONTROL.JDIS
bit is set.
The RBRK bit can be used to detect J1850 bus
shorted high conditions. If RBRK is read as a logic
high multiple times before an EOFM occurs, then a
possible bus shorted high condition exists. The
user program can take appropriate measures to
test the bus if this condition occurs. Note that this
bit does not necessarily clear when ERROR is
read.
J1850 Byte Level Protocol Decoder (JBLPD)
0: No valid Break symbol received
1: Valid Break symbol received
Bit 2 = CRCE Cyclic Redundancy Check Error
The receiver section always keeps a running tab of
the CRC of all data bytes received from the VPWl
since the last EOD symbol. The CRC check is per-
formed when a valid EOD symbol is received both
after a message string (subsequent to an SOF
symbol) and after an IFR3 string (subsequent to
an NB0 symbol). If the received CRC check fails,
then the CRCE bit is set to a logic one. CRC errors
are inhibited if the JBLPD peripheral is in the
“sleep or filter and NOT presently transmitting”
mode. A CRC error occurs once for a frame. After-
wards, the receiver is disabled until an EOFM
symbol is received and queued transmits for the
present frame are cancelled (but the TRA bit is not
set). CRCE is cleared when ERROR is read. It is
also cleared while the CONTROL.JE bit is reset or
while the CONTROL.JDIS bit is set, or on reset.
0: No CRC error detected
1: CRC error detected
Bit 1 = IFD Invalid Frame Detect
The IFD bit gets set when the following conditions
are detected from the filtered VPWI pin:
– An SOF symbol is received after an EOD mini-
– An SOF symbol is received when expecting data
– If NFL = 0 and a message frame greater than 12
– An EOD minimum time has elapsed when data
– A logic 0 or 1 symbol is received (active for Tv1
– The second EODM symbol received in a frame
IFD errors are inhibited if the JBLPD peripheral is
in the “sleep or filter and NOT presently transmit-
ting” mode. An IFD error occurs once for a frame.
Afterwards, the receiver is disabled until an EOFM
symbol is received, and queued transmits for the
present frame are cancelled (but the TRA bit is not
set). IFD is cleared when ERROR is read. It is also
cleared while the CONTROL.JE bit is reset or
while the CONTROL.JDIS bit is set or on reset.
0: No invalid frame detected
1: Invalid frame detected
mum, but before an EOF minimum.
bits.
bytes (i.e. 12 bytes plus one bit) has been re-
ceived in one frame.
bits are expected.
or Tv2) when an SOF was expected.
is NOT followed directly by an EOFM symbol.
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