MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 136

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pulse-Width Modulator (PWM)
11.2.12 PWM Control Register
Read: Anytime
Write: Anytime
PSWAI — PWM Halts While in Wait Mode Bit
CENTR — Center-Aligned Output Mode Bit
RDPP — Reduced Drive of Port P Bit
PUPP — Pullup Port P Enable Bit
PSBCK — PWM Stops While in Background Mode Bit
136
To avoid irregularities in the PWM output mode, write the CENTR bit only when PWM channels are
disabled.
0 = Continue PWM main clock generator while in wait mode.
1 = Halt PWM main clock generator when the part is in wait mode.
0 = PWM channels operate in left-aligned output mode.
1 = PWM channels operate in center-aligned output mode.
0 = Full drive for all port P output pins
1 = Reduced drive for all port P output pins
0 = Disable port P pullups
1 = Enable pullups for all port P input pins.
0 = Allows PWM to continue while in background mode
1 = Disable PWM input clock while in background mode.
Address: $0054
Reset:
Read:
Write:
Bit 7
0
0
Figure 11-24. PWM Control Register (PWCTL)
= Unimplemented
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
5
0
0
PSWAI
4
0
CENTR
3
0
RDPP
2
0
PUPP
1
0
Freescale Semiconductor
PSBCK
Bit 0
0