MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 291

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 18-1
The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling
edge to where the target perceives the beginning of the bit time. Ten target E cycles later, the target
senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin
during host-to-target transmissions to speed up rising edges. Since the target does not drive the BKGD
pin during this period, there is no need to treat the line as an open-drain signal during host-to-target
transmissions.
Figure 18-2
the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the
perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the
target to recognize it (at least two target E cycles). The host must release the low drive before the target
MCU drives a brief active-high speed-up pulse seven cycles after the perceived start of the bit time. The
host should sample the bit level about 10 cycles after it started the bit time.
Freescale Semiconductor
TARGET MCU
TARGET MCU
BKGD PIN
SPEEDUP
BKGD PIN
PERCEIVED
DRIVE TO
TRANSMIT 1
TRANSMIT 0
OF BIT TIME
E CLOCK
TARGET
PULSE
E CLOCK
HOST
START OF BIT
MCU
START
PERCEIVED
HOST
HOST
SYNCHRONIZATION
shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target M68HC12 MCU.
UNCERTAINTY
shows the host receiving a logic 1 from the target MCU. Since the host is asynchronous to
TIME
Figure 18-2. BDM Target to Host Serial Bit Timing (Logic 1)
HIGH IMPEDANCE
Figure 18-1. BDM Host to Target Serial Bit Timing
R-C RISE
10 CYCLES
M68HC12B Family Data Sheet, Rev. 9.1
10 CYCLES
10 CYCLES
TARGET SENSES BIT
HIGH IMPEDANCE
HOST SAMPLES
BKGD PIN
HIGH IMPEDANCE
Background Debug Mode (BDM)
EARLIEST
START OF
NEXT BIT
EARLIEST
START OF
NEXT BIT
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