MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 244

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.1 Background
Modern application layer software is built on two fundamental assumptions:
This behavior cannot be achieved with a single transmit buffer. That buffer must be reloaded right after
the previous message has been sent. This loading process lasts a definite amount of time and has to be
completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages.
Even if this is feasible for limited CAN bus speeds, it requires that the central processor unit (CPU) reacts
with short latencies to the transmit interrupt.
A double buffer scheme would decouple the reloading of the transmit buffers from the actual message
being sent and as such reduces the reaction requirements on the CPU. Problems may arise if the sending
of a message would be finished just while the CPU reloads the second buffer. In that case, no buffer would
then be ready for transmission and the bus would be released.
At least three transmit buffers are required to meet the first requirement under all circumstances. The
msCAN12 has three transmit buffers.
The second requirement calls for some sort of internal priorization which the msCAN12 implements with
the “local priority” concept described here.
244
msCAN12 Controller
1. Any CAN node is able to send out a stream of scheduled messages without releasing the bus
2. The internal message queue within any CAN node is organized so that the highest priority
between two messages. Such nodes will arbitrate for the bus right after sending the previous
message and will only release the bus in case of lost arbitration.
message will be sent out first if more than one message is ready to be sent.
Figure 16-1. Typical CAN System with msCAN12
CAN SYSTEM
CAN STATION 1
TxCAN
CONTROLLER
M68HC12B Family Data Sheet, Rev. 9.1
msCAN12
TRANSCEIVER
RxCAN
CAN
CAN STATION 2
. . .
CAN STATION N
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