MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 186

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Capture Timer (ECT) Module
PBOVF — Pulse Accumulator B Overflow Flag
13.4.25 8-Bit Pulse Accumulators Holding Registers
Read: Anytime
Write: Anytime
These registers are used to latch the value of the corresponding pulse accumulator when the related bits
in register ICPACR ($A8) are enabled (see
186
This bit is set when the 16-bit pulse accumulator B overflows from $FFFF to $0000 or when 8-bit pulse
accumulator 1 (PAC1) overflows from $FF to $00. This bit is cleared by a write to the PBFLG register
with bit 1 set. Any access to the PACN1 and PACN0 registers will clear the PBOVF flag in this register
when TFFCA bit in register TSCR ($86) is set.
Address: $00B2
Address: $00B3
Address: $00B4
Address: $00B5
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Figure 13-46. 8-Bit Pulse Accumulator Holding Register 3 (PA3H)
Figure 13-47. 8-Bit Pulse Accumulator Holding Register 2 (PA2H)
Figure 13-48. 8-Bit Pulse Accumulator Holding Register 1 (PA1H)
Figure 13-49. 8-Bit Pulse Accumulator Holding Register 0 (PA0H)
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
Bit 6
Bit 6
Bit 6
Bit 6
6
0
6
0
6
0
6
0
M68HC12B Family Data Sheet, Rev. 9.1
Bit 5
Bit 5
Bit 5
Bit 5
5
0
5
0
5
0
5
0
13.3.2 Pulse
Bit 4
Bit 4
Bit 4
Bit 4
4
0
4
0
4
0
4
0
Accumulators).
Bit 3
Bit 3
Bit 3
Bit 3
3
0
3
0
3
0
3
0
Bit 2
Bit 2
Bit 2
Bit 2
2
0
2
0
2
0
2
0
Bit 1
Bit 1
Bit 1
Bit 1
1
0
1
0
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0