MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 272

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.12.11 msCAN12 Transmit Error Counter
This register reflects the status of the msCAN12 transmit error counter. The register is read only.
16.12.12 msCAN12 Identifier Acceptance Registers
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message will be overwritten by the next message (dropped).
The acceptance registers of the msCAN12 are applied on the IDR0 to IDR3 registers of incoming
messages in a bit-by-bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only
the first two (CIDMR0/CIDMR1 and CIDAR0/CIDAR1) are applied.
272
msCAN12 Controller
Address: $010F
Address: $0110
Address: $0111
Address: $0112
Address: $0113
Both error counters may be read only when in sleep or soft-reset mode.
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Figure 16-26. msCAN12 Transmit Error Counter (CTXERR)
Figure 16-27. First Bank msCAN12 Identifier Acceptance
TXERR7
Bit 7
Bit 7
AC7
Bit 7
AC7
Bit 7
AC7
Bit 7
AC7
0
= Unimplemented
TXERR6
AC6
AC6
AC6
AC6
6
0
6
6
6
6
M68HC12B Family Data Sheet, Rev. 9.1
Registers (CIDAR0–CIDAR3)
TXERR5
AC5
AC5
AC5
AC5
5
0
5
5
5
5
NOTE
TXERR4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
AC4
AC4
AC4
AC4
4
0
4
4
4
4
TXERR3
AC3
AC3
AC3
AC3
3
0
3
3
3
3
TXERR2
AC2
AC2
AC2
AC2
2
0
2
2
2
2
TXERR1
AC1
AC1
AC1
AC1
1
0
1
1
1
1
Freescale Semiconductor
TXERR0
Bit 0
Bit 0
AC0
Bit 0
AC0
Bit 0
AC0
Bit 0
AC0
0