MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 230

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Byte Data Link Communications (BDLC)
that contains an indefinite number of data bytes. All other features of the frame remain the same, including
the SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first inform all other nodes on the network
that this is about to happen. This is usually accomplished by sending a special predefined message.
15.8.5.3 Transmitting a Message in Block Mode
A block mode message is transmitted inherently by simply loading the bytes one by one into the BDR until
the message is complete. The programmer should wait until the TDRE flag (see
15.9.3 BDLC State
Vector
Register) is set prior to writing a new byte of data into the BDR. The BDLC does not contain any
predefined maximum J1850 message length requirement.
15.8.5.4 J1850 Bus Errors
The BDLC detects several types of transmit and receive errors which can occur during the transmission
of a message onto the J1850 bus.
Transmission error — If the message transmitted by the BDLC contains invalid bits or framing symbols
on non-byte boundaries, this constitutes a transmission error. When a transmission error is detected, the
BDLC immediately ceases transmitting. The error condition is reflected in the BSVR (see
Table
15-1). If
the interrupt enable bit (IE in BCR1) is set, a CPU interrupt request from the BDLC is generated.
CRC error — A cyclical redundancy check (CRC) error is detected when the data bytes and CRC byte of
a received message are processed and the CRC calculation result is not equal. The CRC code detects
any single and 2-bit errors, as well as all 8-bit burst errors and almost all other types of errors. The CRC
error flag (in BSVR) is set when a CRC error is detected. (See
15.9.3 BDLC State Vector
Register.)
Symbol error — A symbol error is detected when an abnormal (invalid) symbol is detected in a message
being received from the J1850 bus. The invalid symbol is set when a symbol error is detected. (See
15.9.3
BDLC State Vector
Register.)
Framing error — A framing error is detected if an EOD or EOF symbol is detected on a non-byte
boundary from the J1850 bus. A framing error also is detected if the BDLC is transmitting the EOD and
instead receives an active symbol. The symbol invalid, or the out-of-range flag, is set when a framing error
is detected. (See
15.9.3 BDLC State Vector
Register.)
Bus fault — If a bus fault occurs, the response of the BDLC depends upon the type of bus fault.
If the bus is shorted to battery, the BDLC waits for the bus to fall to a passive state before it attempts to
transmit a message. As long as the short remains, the BDLC never attempts to transmit a message onto
the J1850 bus.
If the bus is shorted to ground, the BDLC sees an idle bus, begins to transmit the message, and then
detects a transmission error (in BSVR), since the short to ground does not allow the bus to be driven to
the active (dominant) SOF state. The BDLC aborts that transmission and waits for the next CPU
command to transmit.
In any case, if the bus fault is temporary, as soon as the fault is cleared, the BDLC resumes normal
operation. If the bus fault is permanent, it may result in permanent loss of communication on the J1850
bus. (See
15.9.3 BDLC State Vector
Register.)
BREAK — If a BREAK symbol is received while the BDLC is transmitting or receiving, an invalid symbol
(in BSVR) interrupt is generated. Reading the BSVR (see
15.9.3 BDLC State Vector
Register) clears this
interrupt condition. The BDLC waits for the bus to idle, then waits for a start-of-frame (SOF) symbol.
M68HC12B Family Data Sheet, Rev. 9.1
230
Freescale Semiconductor