MCHC912B32CFUE8 Freescale Semiconductor, MCHC912B32CFUE8 Datasheet - Page 258

• Manufacturer Part Number: MCHC912B32CFUE8
• Description: IC MCU 32K FLASH 8MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MCHC912B32CFUE8

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 768 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Package: 80PQFP
• Family Name: HC12
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 63
• Processor Series: HC912B
• Core: HC12
• Data Ram Size: 1 KB
• Maximum Clock Frequency: 8 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: M68EVB912B32E
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.11.2 Identifier Registers
The Bosch CAN 2.0A and 2.0B protocol specifications allow for two different sizes of message identifiers.
The Bosch CAN 2.0A specification requires an 11-bit identifier in the message buffer and the Bosch CAN
2.0B specification requires a 29-bit identifier in the message buffer. The resulting message buffers are
referred to as standard and extended formats, respectively.
The identifier registers (IDRn) in the memory map can be configured to create either the 11-bit
(IDR10–IDR0) identifier necessary for the standard format or the 29-bit (IDR28–IDR0) identifier
necessary for the extended format.
while
significant bit and is transmitted first on the bus during the arbitration procedure. The priority of an
identifier is defined to be the highest for the smallest binary number.
258
msCAN12 Controller
Figure 16-12
details the identifier structure used in the extended format. ID10/ID28 is the most
Address
1. x is 4, 5, 6, or 7 depending on which buffer, RxFG, Tx0,
2. Not applicable for receive buffers.
Figure 16-10. Message Buffer Organization
01xC
01xD
01x0
01x1
01x2
01x3
01x4
01x5
01x6
01x7
01x8
01x9
01xA
01xB
01xE
01xF
Tx1, or Tx2, respectively.
(1)
Figure 16-11
M68HC12B Family Data Sheet, Rev. 9.1
TRANSMIT BUFFER PRIORITY REGISTER
DATA SEGMENT REGISTER 0
DATA SEGMENT REGISTER 1
DATA SEGMENT REGISTER 2
DATA SEGMENT REGISTER 3
DATA SEGMENT REGISTER 4
DATA SEGMENT REGISTER 5
DATA SEGMENT REGISTER 6
DATA SEGMENT REGISTER 7
details the identifier structure used in the standard format
DATA LENGTH REGISTER
IDENTIFIER REGISTER 0
IDENTIFIER REGISTER 1
IDENTIFIER REGISTER 2
IDENTIFIER REGISTER 3
Register Name
UNUSED
UNUSED
(2)
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