DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 11

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.6
5.7
5.8
Section 6 Interrupt Controller (INTC) ...............................................................105
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
5.5.1
5.5.2
5.5.3
5.5.4
Cases when Exceptions are Accepted .................................................................................. 99
Stack States after Exception Handling Ends ...................................................................... 100
Usage Notes ....................................................................................................................... 102
5.8.1
5.8.2
5.8.3
5.8.4
Features.............................................................................................................................. 105
Input/Output Pins ............................................................................................................... 107
Register Descriptions ......................................................................................................... 108
6.3.1
6.3.2
6.3.3
6.3.4
Interrupt Sources................................................................................................................ 121
6.4.1
6.4.2
6.4.3
Interrupt Exception Handling Vector Table....................................................................... 123
Interrupt Operation............................................................................................................. 127
6.6.1
6.6.2
Interrupt Response Time.................................................................................................... 130
Data Transfer with Interrupt Request Signals .................................................................... 132
6.8.1
6.8.2
6.8.3
6.8.4
Usage Note......................................................................................................................... 134
Types of Exceptions Triggered by Instructions ...................................................... 97
Trap Instructions ..................................................................................................... 97
Illegal Slot Instructions ........................................................................................... 98
General Illegal Instructions..................................................................................... 98
Value of Stack Pointer (SP) .................................................................................. 102
Value of Vector Base Register (VBR) .................................................................. 102
Address Errors Caused by Stacking for Address Error Exception Handling ........ 102
Notes on Slot Illegal Instruction Exception Handling .......................................... 103
Interrupt Control Register 0 (ICR0)...................................................................... 109
IRQ Control Register (IRQCR) ............................................................................ 110
IRQ Status register (IRQSR) ................................................................................ 113
Interrupt Priority Registers A to F and H to M
(IPRA to IPRF and IPRH to IPRM)...................................................................... 118
External Interrupts ................................................................................................ 121
On-Chip Peripheral Module Interrupts ................................................................. 122
User Break Interrupt ............................................................................................. 122
Interrupt Sequence ................................................................................................ 127
Stack after Interrupt Exception Handling ............................................................. 130
Handling Interrupt Request Signals as Sources
for DTC Activation and CPU Interrupts, but Not DMAC Activation .................. 133
Handling Interrupt Request Signals as Sources
for DMAC Activation, but Not CPU Interrupts and DTC Activation .................. 134
Handling Interrupt Request Signals as Sources
for DTC Activation, but Not CPU Interrupts and DMAC Activation .................. 134
Handling Interrupt Request Signals as Sources
for CPU Interrupts, but Not DTC and DMAC Activation .................................... 134
Rev. 3.00 May 17, 2007 Page xi of lviii