DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 449

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit
11 to 8 RS[3:0]
7
6
Bit Name
DL
DS
Initial
Value
0000
0
0
R/W
R/W
R/W
R/W
Descriptions
Resource Select 3 to 0
Specify which transfer requests will be sent to the DMAC.
The changing of transfer request source should be done
in the state that the DMA enable bit (DE) is set to 0.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DREQ Level and DREQ Edge Select
Specify the detecting method of the DREQ pin input and
the detecting level.
If the transfer request source is specified as an on-chip
peripheral module or if an auto-request is specified, these
bits are invalid.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Section 10 Direct Memory Access Controller (DMAC)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
External request, dual address mode
Setting prohibited
External request, single address mode
External address space → External device with
DACK
External request, single address mode
External device with DACK → External address
space
Auto request
Setting prohibited
MTU2 (TGIA_0)
MTU2 (TGIA_1)
MTU2 (TGIA_2)
MTU2 (TGIA_3)
MTU2 (TGIA_4)
A/D_1 (ADI_1)
SCI_0 (TXI_0)
SCI_0 (RXI_0)
SCI_1 (TXI_1)
SCI_1 (RXI_1)
Rev. 3.00 May 17, 2007 Page 391 of 1582
REJ09B0181-0300