DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 850

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3
The SCIF has the following registers. These registers specify the data format and bit rate, and
control the transmitter and receiver sections.
Table 16.2 Register Configuration
16.3.1
SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order
received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,
it is automatically transferred to SCFRDR, the receive FIFO data register. The CPU cannot read or
write to SCRSR directly.
Rev. 3.00 May 17, 2007 Page 792 of 1582
REJ09B0181-0300
Register Name
Serial mode register_3
Bit rate register_3
Serial control register_3
Transmit FIFO data register_3
Serial status register_3
Receive FIFO data register_3
FIFO control register_3
FIFO data count register_3
Serial port register_3
Line status register_3
Register Descriptions
Receive Shift Register (SCRSR)
Initial value:
R/W:
Bit:
Abbr.
SCSMR_3
SCBRR_3
SCSCR_3
SCFTDR_3 W
SCFSR_3
SCFRDR_3 R
SCFCR_3
SCFDR_3
SCSPTR_3 R/W
SCLSR_3
7
-
-
6
-
-
5
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
4
-
-
Initial Value
H'0000
H'FF
H'0000
H'xx
H'0060
H'xx
H'0000
H'0000
H'00xx
H'0000
3
-
-
2
-
-
1
-
-
Address
H'FFFFC180
H'FFFFC182
H'FFFFC184
H'FFFFC186
H'FFFFC188
H'FFFFC18A
H'FFFFC18C
H'FFFFC18E
H'FFFFC190
H'FFFFC192
0
-
-
Access Size
16
8
16
8
16
8
16
16
16
16