MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 217

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2 Programming Model
The following sections describe the registers incorporated into the SIM.
6.2.1 SIM Register Memory Map
Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM
are memory-mapped registers offset from the MBAR address pointer defined in
MBAR[BA]. This supervisor-level register is described in Section 6.2.2, “Module Base
Address Register (MBAR).” Because SIM registers depend on the base address defined in
MBAR[BA], MBAR must be programmed before SIM registers can be accessed.
0x010–
MBAR
Offset
0x00C
0x03C
0x000
0x004
0x008
0x040
0x044
0x048
Default bus master park
PLL control (PLLCR)
Reset status register
register (MPARK)
Although external masters cannot access the MCF5407’s
on-chip memories or MBAR, they can access any of the SIM
memory map and peripheral registers, such as those belonging
to the interrupt controller, chip-select module, UARTs, timers,
DMA, and I
(RSR) [p. 6-5]
Pin assignment register (PAR) [p. 6-10]
[p. 6-11]
[31:24]
[p. 7-3]
2
C.
Interrupt Control Registers (ICRs) [p. 9-3]
Interrupt Controller Registers [p. 9-2]
Table 6-1. SIM Registers
System protection
(SYPCR) [p. 6-8]
Chapter 6. SIM Overview
control register
Interrupt pending register (IPR) [p. 9-6]
Interrupt mask register (IMR) [p. 9-6]
Reserved
[23:16]
NOTE:
Reserved
interrupt vector register
assignment register
Software watchdog
(IRQPAR) [p. 9-7]
(SWIVR) [p. 6-9]
Interrupt port
Reserved
Reserved
[15:8]
service register (SWSR)
Programming Model
Software watchdog
Autovector register
(AVR) [p. 9-5]
Reserved
[p. 6-9]
[7:0]
6-3