MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 6

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
1.4.3
1.4.4
2.1
2.1.1
2.1.2
2.1.2.1
2.1.2.1.1
2.1.2.2
2.1.2.2.1
2.1.2.2.2
2.1.2.2.3
2.1.2.3
2.1.3
2.2
2.2.1
2.2.1.1
2.2.1.2
2.2.1.3
2.2.1.4
2.2.1.5
2.2.1.6
2.2.2
2.2.2.1
2.2.2.2
2.2.2.3
2.2.2.4
2.2.2.5
2.2.2.6
2.3
2.4
2.4.1
2.4.2
2.5
2.6
2.6.1
vi
Features and Enhancements................................................................................ 2-1
Programming Model ........................................................................................... 2-7
Integer Data Formats......................................................................................... 2-13
Organization of Data in Registers..................................................................... 2-13
Addressing Mode Summary ............................................................................. 2-15
Instruction Set Summary................................................................................... 2-15
Supervisor Registers ..................................................................................... 1-16
Instruction Set ............................................................................................... 1-16
Clock-Multiplied Microprocessor Core.......................................................... 2-2
Enhanced Pipelines ......................................................................................... 2-2
Debug Module Enhancements ........................................................................ 2-6
User Programming Model .............................................................................. 2-8
Supervisor Programming Model................................................................... 2-10
Organization of Integer Data Formats in Registers ...................................... 2-13
Organization of Integer Data Formats in Memory ....................................... 2-14
Additions to the Instruction Set Architecture ............................................... 2-18
Instruction Fetch Pipeline (IFP).................................................................. 2-4
Operand Execution Pipeline (OEP) ............................................................ 2-4
Harvard Memory Architecture ................................................................... 2-6
Data Registers (D0–D7) ............................................................................. 2-8
Address Registers (A0–A6) ........................................................................ 2-9
Stack Pointer (A7, SP) ................................................................................ 2-9
Program Counter (PC) ................................................................................ 2-9
Condition Code Register (CCR) ................................................................. 2-9
MAC Programming Model....................................................................... 2-10
Status Register (SR).................................................................................. 2-11
Vector Base Register (VBR) .................................................................... 2-12
Cache Control Register (CACR) .............................................................. 2-12
Access Control Registers (ACR0–ACR3)................................................ 2-12
RAM Base Address Registers (RAMBAR0 and RAMBAR1) ................ 2-12
Module Base Address Register (MBAR) ................................................. 2-12
Branch Acceleration ............................................................................... 2-4
Illegal Opcode Handling......................................................................... 2-5
Hardware Multiply/Accumulate (MAC) Unit ........................................ 2-5
Hardware Divide Unit............................................................................. 2-6
MCF5407 Processor Core
MCF5407 User’s Manual
CONTENTS
ColdFire Core
Chapter 2
Part I
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