MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 245

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 8-5 describes I2SR fields.
8.5.5 I
In master-receive mode, reading the I2DR, Figure 8-9, allows a read to occur and initiates
7
6
5
4
3
2
1
0
Bits
ICF
IAAS
IBB
IAL
—
SRW
IIF
RXAK
Name
Address
2
Reset
Field
C Data I/O Register (I2DR)
R/W
Data transferring bit. While one byte of data is transferred, ICF is cleared.
0 Transfer in progress
1 Transfer complete. Set by the falling edge of the ninth clock of a byte transfer.
I
SRW and set its TX/RX mode accordingly. Writing to I2CR clears this bit.
0 Not addressed.
1 Addressed as a slave. Set when its own address (IADR) matches the calling address.
I
0 Bus is idle. If a STOP signal is detected, IBB is cleared.
1 Bus is busy. When START is detected, IBB is set.
Arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by
writing zero to it.)
Reserved, should be cleared.
Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling
address sent from the master. SRW is valid only when a complete transfer has occurred, no other
transfers have been initiated, and the I
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
I
0 No I
1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of
Received acknowledge. The value of SDA during the acknowledge bit of a bus cycle.
0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus
1 No acknowledge signal was detected at the ninth clock.
2
2
2
C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check
C bus busy bit. Indicates the status of the bus.
C interrupt. Must be cleared by software by writing a zero to it in the interrupt routine.
• SDA sampled low when the master drives high during an address or data-transmit cycle.
• SDA sampled low when the master drives high during the acknowledge bit of a data-receive
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
• Complete one byte transfer (set at the falling edge of the ninth clock)
• Reception of a calling address that matches its own specific address in slave-receive mode
• Arbitration lost
the following occurs:
cycle.
ICF
2
7
C interrupt pending
Figure 8-8. I
IAAS
Table 8-5. I2SR Field Descriptions
R
6
Chapter 8. I
IBB
5
2
CR Status Register (I2SR)
R/W
MBAR + 0x28C
2
IAL
C module is a slave and has an address match.
4
1000_0001
2
C Module
Description
—
3
R
SRW
2
R/W
IIF
1
Programming Model
RXAK
R
0
8-9