MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 358

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Descriptions
Figure 14-13 shows the configuration of URB1.
14.3.12 UART Transmitter Buffers (UTBn)
The transmitter buffer for UART0 consists of the transmitter holding register and the
transmitter shift register. The holding register accepts characters from the bus master if
channel’s USRn[TxRDY] is set. A write to the transmitter buffer clears TxRDY, inhibiting
any more characters until the shift register can accept more data. When the shift register is
empty, it checks if the holding register has a valid character to be sent (TxRDY = 0). If there
is a valid character, the shift register loads it and sets USRn[TxRDY] again. Writes to the
transmitter buffer when the channel’s TxRDY = 0 and when the transmitter is disabled have
no effect on the transmitter buffer.
Figure 14-14 shows UTB0. TB contains the character in the transmitter buffer.
The transmitter buffer in UART1 consists of the transmitter shift register and the Tx FIFO,
as described in Section 14.5.2.6, “FIFOs in UART1.” The Tx FIFO in UART1 accepts
characters/samples from the bus master if there is room for them in the FIFO. A write to the
transmitter buffer clears TxRDY if the number of bytes in the FIFO exceeds the threshold
level in TXLVL. When the shift register is empty, it checks if the FIFO has a valid
character/sample to be sent. Valid characters are loaded into the shift register. Unlike UART
14-16
Address
Address
Address
Reset
Reset
Reset
Field
Field
Field
R/W
R/W
R/W
31
7
7
Figure 14-14. UART Transmitter Buffer for UART0 (UTB0)
RB[31:24]
Figure 14-12. UART Receiver Buffer for UART0 (URB0)
Figure 14-13. UART Receiver Buffer for UART1 (URB1)
24
23
0000_0000_0000_0000_0000_0000_0000_0000
MCF5407 User’s Manual
RB[23:16]
MBAR + 0x1CC
MBAR + 0x1CC
MBAR + 0x20C
0000_0000
0000_0000
Read only
Read only
Write only
16
RB
TB
15
RB[15:8]
8
7
RB[7:0]
0
0
0