MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 448

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bus Arbitration
18.8 Bus Arbitration
The MCF5407 bus protocol gives either the MCF5407 or an external device access to the
external bus. If more than one external device uses the bus, an external arbiter can prioritize
requests and determine which device is bus master. When the MCF5407 is bus master, it
uses the bus to fetch instructions and transfer data to and from external memory. When an
external device is bus master, the MCF5407 can monitor the external master’s transfers and
interact through its chip-select, DRAM control, and transfer termination signals. See
Section 10.4.1.3, “Chip-Select Control Registers (CSCR0–CSCR7),” and Chapter 11,
“Synchronous/Asynchronous DRAM Controller Module.”
Two-wire bus arbitration is used where the MCF5407 shares the bus with a single external
device. This mode uses BG and BD. The external device can ignore BR. Three-wire mode
is used where the MCF5407 shares the bus with multiple external devices. This requires an
external bus arbiter and uses BG, BD, and BR. In either mode, the MCF5407 bus arbiter
operates synchronously and transitions between states on the rising edge of CLKIN.
Table 18-6 shows the four arbitration states the MCF5407 can be in during bus operation.
18-20
Reset
Implicit
master
State
1.
2.
3.
4.
5.
6.
7.
1.
2.
1.
2.
Drive 0x7FFFFF on A[31:5]
Drive 0x0 on A[1:0]
Drive interrupt level on A[4:2]
Drive R/W to read (R/W = 1)
Drive SIZ[1:0] to indicate byte (SIZ[1:0] = 01)
Drive TT[1:0] and TM[2:0] to indicate interrupt
acknowledge (TT[1:0] = 11; TM[2:0] = interrupt
level)
Assert TS for one CLKIN cycle
Negate TS
Drive TM[2:0] to indicate interrupt
acknowledge (TM[2:0] = interrupt level)
Read and store data (D[31:24])
Recognize the transfer is done
MCF5407
Master
None
Figure 18-23. Interrupt-Acknowledge Cycle Flowchart
MCF5407
driven
driven
Table 18-6. MCF5407 Arbitration Protocol States
Bus
Not
Not
Negated The MCF5407 enters reset state from any other state when RSTI or
Negated The MCF5407 is bus master (BG input is asserted) but is not ready to
BD
software watchdog reset is asserted. If both are negated, the MCF5407
enters implicit or external device mastership state, depending on BG.
begin a bus cycle. It continues to three-state the bus until an internal bus
request.
MCF5407 User’s Manual
1.
2.
3.
Decode address and select the appropriate slave
device.
Drive data on D[31:24]
Assert TA for one CLKIN cycle
Description
SYSTEM